Issued Patents All Time
Showing 251–275 of 295 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5401681 | Method of forming a bit line over capacitor array of memory cells | — | 1995-03-28 |
| 5397908 | Arrays of memory integrated circuitry | Trung T. Doan | 1995-03-14 |
| 5393683 | Method of making semiconductor devices having two-layer gate structure | Viju K. Mathews, Pierre C. Fazan, Roy L. Maddox, III, Akram Ditali | 1995-02-28 |
| 5391511 | Semiconductor processing method of producing an isolated polysilicon lined cavity and a method of forming a capacitor | Trung T. Doan | 1995-02-21 |
| 5371701 | Stacked delta cell capacitor | Ruojia Lee, Yauh-Ching Liu, Pierre C. Fazan, Steven D. Cummings | 1994-12-06 |
| 5362666 | Method of producing a self-aligned contact penetrating cell plate | — | 1994-11-08 |
| 5348899 | Method of fabricating a bottom and top gated thin film transistor | Monte Manning | 1994-09-20 |
| 5346587 | Planarization of a gate electrode for improved gate patterning over non-planar active area isolation | Trung T. Doan | 1994-09-13 |
| 5340763 | Multi-pin stacked capacitor utilizing micro villus patterning in a container cell and method to fabricate same | — | 1994-08-23 |
| 5340765 | Method for forming enhanced capacitance stacked capacitor structures using hemi-spherical grain polysilicon | Randhir P. S. Thakur | 1994-08-23 |
| 5338700 | Method of forming a bit line over capacitor array of memory cells | Aftab Ahmad | 1994-08-16 |
| 5334862 | Thin film transistor (TFT) loads formed in recessed plugs | Monte Manning | 1994-08-02 |
| 5330879 | Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer | — | 1994-07-19 |
| 5321649 | Stacked delta cell capacitor | Ruojia Lee, Yauh-Ching Liu, Pierre C. Fazan, Steven D. Cummings | 1994-06-14 |
| 5321648 | Stacked V-cell capacitor using a disposable outer digit line spacer | Pierre C. Fazan, Ruojia Lee, Yauh-Ching Liu | 1994-06-14 |
| 5292683 | Method of isolating semiconductor devices and arrays of memory integrated circuitry | Trung T. Doan | 1994-03-08 |
| 5292677 | Reduced mask CMOS process for fabricating stacked capacitor multi-megabit dynamic random access memories utilizing single etch stop layer for contacts | — | 1994-03-08 |
| 5272367 | Fabrication of complementary n-channel and p-channel circuits (ICs) useful in the manufacture of dynamic random access memories (drams) | Tyler Lowrey | 1993-12-21 |
| 5270241 | Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing | Michael A. Walker | 1993-12-14 |
| 5266513 | Method of making stacked W-cell capacitor | Pierre C. Fazan, Ruojia Lee, Yauh-Ching Liu | 1993-11-30 |
| 5262343 | DRAM stacked capacitor fabrication process | Howard E. Rhodes, Pierre C. Fazan, Hiang C. Chan, Yauh-Ching Liu | 1993-11-16 |
| 5250457 | Method of forming a buried bit line array of memory cells | — | 1993-10-05 |
| 5244837 | Semiconductor electrical interconnection methods | — | 1993-09-14 |
| 5236855 | Stacked V-cell capacitor using a disposable outer digit line spacer | Pierre C. Fazan, Ruojia Lee, Yauh-Ching Liu | 1993-08-17 |
| 5234855 | Stacked comb spacer capacitor | Howard E. Rhodes, Hiang C. Chan, Yauh-Ching Liu, Pierre C. Fazan, Gurtej S. Sandhu | 1993-08-10 |