Issued Patents All Time
Showing 101–125 of 130 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6120942 | Method for making a photomask with multiple absorption levels | — | 2000-09-19 |
| 6087270 | Method of patterning substrates | Kevin G. Donohoe, Brian A. Vaartstra | 2000-07-11 |
| 6087689 | Memory cell having a reduced active area and a memory array incorporating the same | — | 2000-07-11 |
| 6083821 | Integrated circuit having a void between adjacent conductive lines | — | 2000-07-04 |
| 6051511 | Method and apparatus for reducing isolation stress in integrated circuits | Randhir P. S. Thakur, Kevin G. Donohoe, Zhiqiang Wu | 2000-04-18 |
| 6005801 | Reduced leakage DRAM storage unit | Zhiqiang Wu, Randhir P. S. Thakur, Kirk D. Prall | 1999-12-21 |
| 5985766 | Semiconductor processing methods of forming a contact opening | Zhiqiang Wu, Manny K. F. Ma | 1999-11-16 |
| 5976947 | Method for forming dielectric within a recess | — | 1999-11-02 |
| 5973954 | Reduced leakage DRAM storage unit | Zhigiang Wu, Randhir P. S. Thakur | 1999-10-26 |
| 5952671 | Small electrode for a chalcogenide switching device and method for fabricating same | Russell C. Zahorik | 1999-09-14 |
| 5920788 | Chalcogenide memory cell with a plurality of chalcogenide electrodes | — | 1999-07-06 |
| 5872048 | Processing methods of forming an electrically conductive plug to a node location | — | 1999-02-16 |
| 5847439 | Integrated circuit having a void between adjacent conductive lines | — | 1998-12-08 |
| 5837564 | Method for optimal crystallization to obtain high electrical performance from chalcogenides | Gurtej S. Sandhu | 1998-11-17 |
| 5789758 | Chalcogenide memory cell with a plurality of chalcogenide electrodes | — | 1998-08-04 |
| 5789277 | Method of making chalogenide memory device | Russell C. Zahorik | 1998-08-04 |
| 5599745 | Method to provide a void between adjacent conducting lines in a semiconductor device | — | 1997-02-04 |
| 5573837 | Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming narrow isolated trenches defined by said masking layer | Ceredig Roberts | 1996-11-12 |
| 5460908 | Phase shifting retical fabrication method | — | 1995-10-24 |
| 5363337 | Integrated circuit memory with variable addressing of memory cells | — | 1994-11-08 |
| 5360992 | Two piece assembly for the selection of pinouts and bond options on a semiconductor device | Tyler Lowrey, Kevin D. Martin | 1994-11-01 |
| 5358908 | Method of creating sharp points and other features on the surface of a semiconductor substrate | Howard E. Rhodes | 1994-10-25 |
| 5254218 | Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming narrow isolated trenches defined by said masking layer | Ceredig Roberts | 1993-10-19 |
| 5142438 | Dram cell having a stacked capacitor with a tantalum lower plate, a tantalum oxide dielectric layer, and a silicide buried contact | Mark E. Tuttle | 1992-08-25 |
| 4676661 | Radioactive timing source for horologic instruments and the like | Joseph Keenan | 1987-06-30 |