Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6603200 | Integrated circuit package | Qwai H. Low, Chok J. Chia | 2003-08-05 |
| 6525421 | Molded integrated circuit package | Chok J. Chia, Wee Liew | 2003-02-25 |
| 6519844 | Overmold integrated circuit package | Kumar Nagarajan, Chok J. Chia | 2003-02-18 |
| 6512293 | Mechanically interlocking ball grid array packages and method of making | Chok J. Chia, Wee Liew | 2003-01-28 |
| 6492253 | Method for programming a substrate for array-type packages | Chok J. Chia, Patrick Variot | 2002-12-10 |
| 6285077 | Multiple layer tape ball grid array package | Chok J. Chia, Qwai H. Low | 2001-09-04 |
| 6225695 | Grooved semiconductor die for flip-chip heat sink attachment | Chok J. Chia, Maniam Alagaratnam | 2001-05-01 |
| 6114189 | Molded array integrated circuit package | Chok J. Chia, Qwai H. Low | 2000-09-05 |
| 6081997 | System and method for packaging an integrated circuit using encapsulant injection | Chok J. Chia, Maniam Alagaratnam | 2000-07-04 |
| 6054767 | Programmable substrate for array-type packages | Chok J. Chia, Patrick Variot | 2000-04-25 |
| 6040632 | Multiple sized die | Qwai H. Low, Chok J. Chia | 2000-03-21 |
| 6002169 | Thermally enhanced tape ball grid array package | Chok J. Chia, Owai H. Low | 1999-12-14 |
| 5981311 | Process for using a removeable plating bus layer for high density substrates | Chok J. Chia, Patrick Variot | 1999-11-09 |
| 5973397 | Semiconductor device and fabrication method which advantageously combine wire bonding and tab techniques to increase integrated circuit I/O pad density | Qwai H. Low, Chok J. Chia | 1999-10-26 |
| 5973393 | Apparatus and method for stackable molded lead frame ball grid array packaging of integrated circuits | Chok J. Chia, Qwai H. Low | 1999-10-26 |
| 5927505 | Overmolded package body on a substrate | Chok J. Chia, Maniam Alagaratnam | 1999-07-27 |
| 5744084 | Method of improving molding of an overmolded package body on a substrate | Chok J. Chia, Maniam Alagaratnam | 1998-04-28 |
| 5643835 | Process for manufacturing and mounting a semiconductor device leadframe having alignment tabs | Chok J. Chia | 1997-07-01 |
| 5594626 | Partially-molded, PCB chip carrier package for certain non-square die shapes | Michael D. Rostoker, Chok J. Chia | 1997-01-14 |
| 5568683 | Method of cooling a packaged electronic device | Chok J. Chia, Manian Alagaratnam, Qwai H. Low | 1996-10-29 |
| 5521427 | Printed wiring board mounted semiconductor device having leadframe with alignment feature | Chok J. Chia | 1996-05-28 |
| 5463529 | High power dissipating packages with matched heatspreader heatsink assemblies | Chok J. Chia, Manian Alagaratnam, Qwai H. Low | 1995-10-31 |
| 5434750 | Partially-molded, PCB chip carrier package for certain non-square die shapes | Michael D. Rostoker, Chok J. Chia | 1995-07-18 |
| 5353193 | High power dissipating packages with matched heatspreader heatsink assemblies | Chok J. Chia, Manian Alagaratnam, Qwai H. Low | 1994-10-04 |
| 5262927 | Partially-molded, PCB chip carrier package | Chok J. Chia | 1993-11-16 |