Issued Patents All Time
Showing 51–75 of 125 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6121794 | High and low voltage compatible CMOS buffer | — | 2000-09-19 |
| 6117736 | Method of fabricating insulated-gate field-effect transistors having different gate capacitances | — | 2000-09-12 |
| 6109775 | Method for adjusting the density of lines and contact openings across a substrate region for improving the chemical-mechanical polishing of a thin-film later disposed thereon | Prabhakar P. Tripathi, Keith K. Chao, Ratan K. Choudhury, Gauri C. Das, Nicholas K. Eib +1 more | 2000-08-29 |
| 6097073 | Triangular semiconductor or gate | Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben +4 more | 2000-08-01 |
| 6005264 | "Microelectronic integrated circuit including hexagonal CMOS ""NAND"" gate device" | — | 1999-12-21 |
| 5985746 | Process for forming self-aligned conductive plugs in multiple insulation levels in integrated circuit structures and resulting product | — | 1999-11-16 |
| 5982659 | Memory cell capable of storing more than two logic states by using different via resistances | V. Swamy Irrinki, Thomas R. Wik, Raymond Leung, Alex Owens | 1999-11-09 |
| 5973376 | Architecture having diamond shaped or parallelogram shaped cells | Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben +4 more | 1999-10-26 |
| 5943576 | Angled implant to build MOS transistors in contact holes | — | 1999-08-24 |
| 5889329 | Tri-directional interconnect architecture for SRAM | Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben +4 more | 1999-03-30 |
| 5877045 | Method of forming a planar surface during multi-layer interconnect formation by a laser-assisted dielectric deposition | — | 1999-03-02 |
| 5872380 | Hexagonal sense cell architecture | Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben +4 more | 1999-02-16 |
| 5867423 | Memory circuit and method for multivalued logic storage by process variations | Alex Owens, Thomas R. Wik, Raymond Leung, V. Swamy Irrinki | 1999-02-02 |
| 5864172 | Low dielectric constant insulation layer for integrated circuit structure and method of making same | Nicholas F. Pasch | 1999-01-26 |
| 5864165 | Triangular semiconductor NAND gate | Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben +4 more | 1999-01-26 |
| 5847990 | Ram cell capable of storing 3 logic states | V. Swamy Irrinki, Raymond Leung, Alex Owens, Thomas R. Wik | 1998-12-08 |
| 5835986 | Electrostatic discharge (ESD) structure and buffer driver structure for providing ESD and latchup protection for integrated circuit structures in minimized I/O space | Hua Wei | 1998-11-10 |
| 5834821 | "Triangular semiconductor ""AND"" gate device" | Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben +4 more | 1998-11-10 |
| 5822214 | CAD for hexagonal architecture | Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben +4 more | 1998-10-13 |
| 5808932 | Memory system which enables storage and retrieval of more than two states in a memory cell | V. Swamy Irrinki, Raymond Leung, Alex Owens, Thomas R. Wik | 1998-09-15 |
| 5808330 | Polydirectional non-orthoginal three layer interconnect architecture | Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben +4 more | 1998-09-15 |
| 5801422 | Hexagonal SRAM architecture | Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben +4 more | 1998-09-01 |
| 5789770 | Hexagonal architecture with triangular shaped cells | Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben +4 more | 1998-08-04 |
| 5789783 | Multilevel metallization structure for integrated circuit I/O lines for increased current capacity and ESD protection | Ratan K. Choudhury, Satish R. Menon | 1998-08-04 |
| 5784328 | Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array | V. Swamy Irrinki, Raymond Leung, Alex Owens, Thomas R. Wik | 1998-07-21 |