Issued Patents All Time
Showing 26–50 of 125 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7633101 | Oxide isolated metal silicon-gate JFET | Madhukar B. Vora | 2009-12-15 |
| 7605031 | Semiconductor device having strain-inducing substrate and fabrication methods thereof | — | 2009-10-20 |
| 7592841 | Circuit configurations having four terminal JFET devices | — | 2009-09-22 |
| 7586155 | Apparatus and method for improving drive-strength and leakage of deep submicron MOS transistors | — | 2009-09-08 |
| 7569873 | Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys | — | 2009-08-04 |
| 7560755 | Self aligned gate JFET structure and method | — | 2009-07-14 |
| 7531854 | Semiconductor device having strain-inducing substrate and fabrication methods thereof | — | 2009-05-12 |
| 7525138 | JFET device with improved off-state leakage current and method of fabrication | Samar K. Saha | 2009-04-28 |
| 7525136 | JFET device with virtual source and drain link regions and method of fabrication | Samar K. Saha | 2009-04-28 |
| 7482642 | Bipolar transistors having controllable temperature coefficient of current gain | — | 2009-01-27 |
| 7474125 | Method of producing and operating a low power junction field effect transistor | — | 2009-01-06 |
| 7453107 | Method for applying a stress layer to a semiconductor device and device formed therefrom | — | 2008-11-18 |
| 7375402 | Method and apparatus for increasing stability of MOS memory cells | — | 2008-05-20 |
| 7224205 | Apparatus and method for improving drive-strength and leakage of deep submicron MOS transistors | — | 2007-05-29 |
| 7071734 | Programmable logic devices with silicon-germanium circuitry and associated methods | — | 2006-07-04 |
| RE38900 | Automating photolithography in the fabrication of integrated circuits | Michael D. Rostoker, Nicholas F. Pasch | 2005-11-29 |
| 6861739 | Minimum metal consumption power distribution network on a bonded die | Azeez Bhavnagarwala | 2005-03-01 |
| 6741122 | Routing technique to adjust clock skew using frames and prongs | Lei Lin | 2004-05-25 |
| 6529400 | Source pulsed, dynamic threshold complementary metal oxide semiconductor static RAM cells | Azeez Bhavnagarwala | 2003-03-04 |
| 6418353 | Automating photolithography in the fabrication of integrated circuits | Michael D. Rostoker, Nicholas F. Pasch | 2002-07-09 |
| 6407434 | Hexagonal architecture | Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben +4 more | 2002-06-18 |
| 6316318 | Angled implant to build MOS transistors in contact holes | — | 2001-11-13 |
| 6312980 | Programmable triangular shaped device having variable gain | Michael D. Rostoker, James S. Koford, Ranko Scepanovic, Edwin R. Jones, Gobi R. Padmanahben +4 more | 2001-11-06 |
| 6303995 | Sidewall structure for metal interconnect and method of making same | Ratan K. Choudhury | 2001-10-16 |
| 6300663 | Insulated-gate field-effect transistors having different gate capacitances | — | 2001-10-09 |