Issued Patents All Time
Showing 1–25 of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10050076 | 3D high resolution X-ray sensor with integrated scintillator grid | — | 2018-08-14 |
| 9754992 | Integrated scintillator grid with photodiodes | Brian Rodricks | 2017-09-05 |
| 9559139 | Integrated scintillator grid with photodiodes | Brian Rodricks | 2017-01-31 |
| 9476991 | 3D high resolution X-ray sensor with integrated scintillator grid | — | 2016-10-25 |
| 9472529 | Apparatus and methods for high-density chip connectivity | — | 2016-10-18 |
| 9466638 | Seemless tiling and high pixel density in a 3D high resolution x-ray sensor with integrated scintillator grid for low noise and high image quality | — | 2016-10-11 |
| 9419046 | Integrated scintillator grid with photodiodes | Brian Rodricks | 2016-08-16 |
| 9219093 | 3D high resolution X-ray sensor with integrated scintillator grid | — | 2015-12-22 |
| 9082869 | Apparatus and methods for high-density chip connectivity | — | 2015-07-14 |
| 8957511 | Apparatus and methods for high-density chip connectivity | — | 2015-02-17 |
| 8042076 | System and method for routing connections with improved interconnect thickness | Payman Zarkesh-Ha, Christopher L. Hamlin, Ashok K. Kapoor, James S. Koford | 2011-10-18 |
| 7968393 | Semiconductor device, design method and structure | — | 2011-06-28 |
| 7964920 | Semiconductor device, design method and structure | — | 2011-06-21 |
| 7745301 | Methods and apparatus for high-density chip connectivity | — | 2010-06-29 |
| 7713804 | Method of forming an oxide isolated metal silicon-gate JFET | Ashok K. Kapoor | 2010-05-11 |
| 7710148 | Programmable switch circuit and method, method of manufacture, and devices and systems including the same | — | 2010-05-04 |
| 7689964 | System and method for routing connections | Payman Zarkesh-Ha, Christopher L. Hamlin, Ashok K. Kapoor, James S. Koford | 2010-03-30 |
| 7645654 | JFET with built in back gate in either SOI or bulk silicon | — | 2010-01-12 |
| 7642566 | Scalable process and structure of JFET for small and decreasing line widths | Ashok K. Kapoor | 2010-01-05 |
| 7633101 | Oxide isolated metal silicon-gate JFET | Ashok K. Kapoor | 2009-12-15 |
| 7557393 | JFET with built in back gate in either SOI or bulk silicon | — | 2009-07-07 |
| 7525163 | Semiconductor device, design method and structure | — | 2009-04-28 |
| 6897520 | Vertically integrated flash EEPROM for greater density and lower cost | — | 2005-05-24 |
| 6025736 | Fast reprogrammable logic with active links between cells | Burnell G. West | 2000-02-15 |
| 6002268 | FPGA with conductors segmented by active repeaters | Paul T. Sasaki, Burnell G. West | 1999-12-14 |