Issued Patents All Time
Showing 101–125 of 125 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5583062 | Self-aligned twin well process having a SiO.sub.2 -polysilicon-SiO.sub.2 barrier mask | — | 1996-12-10 |
| 5543643 | Combined JFET and MOS transistor device, circuit | — | 1996-08-06 |
| 5539246 | "Microelectronic integrated circuit including hexagonal semiconductor ""gate "" device" | — | 1996-07-23 |
| 5523600 | Active device constructed in opening formed in insulation layer | — | 1996-06-04 |
| 5521117 | Process for active device constructed in opening formed in insulation layer with a resistor | — | 1996-05-28 |
| 5521108 | Process for making a conductive germanium/silicon member with a roughened surface thereon suitable for use in an integrated circuit structure | Michael D. Rostoker | 1996-05-28 |
| 5498558 | Integrated circuit structure having floating electrode with discontinuous phase of metal silicide formed on a surface thereof and process for making same | — | 1996-03-12 |
| 5494859 | Low dielectric constant insulation layer for integrated circuit structure and method of making same | — | 1996-02-27 |
| 5472901 | Process for formation of vias (or contact openings) and fuses in the same insulation layer with minimal additional steps | — | 1995-12-05 |
| 5470801 | Low dielectric constant insulation layer for integrated circuit structure and method of making same | Nicholas F. Pasch | 1995-11-28 |
| 5393712 | Process for forming low dielectric constant insulation layer on integrated circuit structure | Michael D. Rostoker, Nicholas F. Pasch | 1995-02-28 |
| 5391505 | Active device constructed in opening formed in insulation layer and process for making same | — | 1995-02-21 |
| 5240511 | Lightly doped polycrystalline silicon resistor having a non-negative temperature coefficient | — | 1993-08-31 |
| 5229307 | Method of making extended silicide and external contact | Madhukar B. Vora, Gregory N. Burton | 1993-07-20 |
| 5227316 | Method of forming self aligned extended base contact for a bipolar transistor having reduced cell size | Madhukar B. Vora, Greg Burton | 1993-07-13 |
| 5166094 | Method of fabricating a base-coupled transistor logic | — | 1992-11-24 |
| 5166767 | Sidewall contact bipolar transistor with controlled lateral spread of selectively grown epitaxial layer | J. Frank Ciacchella | 1992-11-24 |
| 5098854 | Process for forming self-aligned silicide base contact for bipolar transistor | Hemraj K. Hingarh | 1992-03-24 |
| 5061986 | Self-aligned extended base contact for a bipolar transistor having reduced cell size and improved electrical characteristics | Madhukar B. Vora, Greg Burton | 1991-10-29 |
| 5045916 | Extended silicide and external contact technology | Madhukar B. Vor, Gregory N. Burton | 1991-09-03 |
| 4982244 | Buried Schottky clamped transistor | — | 1991-01-01 |
| 4947230 | Base-coupled transistor logic | — | 1990-08-07 |
| 4829363 | Structure for inhibiting dopant out-diffusion | Michael E. Thomas, Madhukar B. Vora | 1989-05-09 |
| 4762801 | Method of fabricating polycrystalline silicon resistors having desired temperature coefficients | — | 1988-08-09 |
| 4640004 | Method and structure for inhibiting dopant out-diffusion | Michael E. Thomas, Madhukar B. Vora | 1987-02-03 |