Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10983758 | System, method, and computer program product for automatically inferring case-split hints in equivalence checking of an electronic design | Rajdeep Mukherjee, Benjamin Chen, Habeeb Farah | 2021-04-20 |
| 10984161 | System, method, and computer program product for sequential equivalence checking in formal verification | Rajdeep Mukherjee, Ravi Prakash, Benjamin Chen, Habeeb Farah | 2021-04-20 |
| 10789404 | System, method, and computer program product for generating a formal verification model | Rajdeep Mukherjee, Benjamin Chen, Habeeb Farah | 2020-09-29 |
| 9460252 | Functional property ranking | Asa Ben-Tzur | 2016-10-04 |
| 9372949 | Guided exploration of circuit design states | Craig Franklin Deaton, Kathryn Drews Kranen, Björn Håkan Hjort, Lars Lundgren | 2016-06-21 |
| 9177089 | Formal verification coverage metrics for circuit design properties | Per Anders M. Franzen, Ross M. Weber, Habeeb Farah, Rajeev Ranjan | 2015-11-03 |
| 9158874 | Formal verification coverage metrics of covered events for circuit design properties | Rajeev Ranjan, Ross M. Weber, Habeeb Farah | 2015-10-13 |
| 8863049 | Constraining traces in formal verification | Lars Lundgren, Chung-Wah Norris Ip, Kathryn Drews Kranen, Lawrence Loh | 2014-10-14 |
| 8826201 | Formal verification coverage metrics for circuit design properties | Per Anders M. Franzen, Ross M. Weber, Habeeb Farah, Rajeev Ranjan | 2014-09-02 |
| 8739092 | Functional property ranking | Asa Ben-Tzur | 2014-05-27 |
| 7730436 | Verification using simultaneous and inductive SAT algorithms | Zurab Khasidashvili, Alexander Nadel, Amit Palti | 2010-06-01 |
| 7159201 | Method and apparatus for cut-point frontier selection and for counter-example generation in formal equivalence verification | John Moondanos, Zurab Khasidashvili | 2007-01-02 |
| 7117465 | Application of the retimed normal form to the formal equivalence verification of abstract RTL descriptions for pipelined designs | Zurab Khasidashvili, John Moondanos | 2006-10-03 |
| 7073141 | Device, system and method for VLSI design analysis | Alexander Novakovsky, Shy Shyman | 2006-07-04 |
| 6792581 | Method and apparatus for cut-point frontier selection and for counter-example generation in formal equivalence verification | John Moondanos, Zurab Khasidashvili | 2004-09-14 |
| 6567959 | Method and device for verification of VLSI designs | Alexander Levin, Carl Seger | 2003-05-20 |
| 6564358 | Method and system for formal verification of a circuit model using binary decision diagrams | John Moondanos, Carl Seger, Daher Kaiss | 2003-05-13 |