Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7730436 | Verification using simultaneous and inductive SAT algorithms | Alexander Nadel, Amit Palti, Ziyad Hanna | 2010-06-01 |
| 7159201 | Method and apparatus for cut-point frontier selection and for counter-example generation in formal equivalence verification | John Moondanos, Ziyad Hanna | 2007-01-02 |
| 7117465 | Application of the retimed normal form to the formal equivalence verification of abstract RTL descriptions for pipelined designs | John Moondanos, Ziyad Hanna | 2006-10-03 |
| 6792581 | Method and apparatus for cut-point frontier selection and for counter-example generation in formal equivalence verification | John Moondanos, Ziyad Hanna | 2004-09-14 |