Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7159201 | Method and apparatus for cut-point frontier selection and for counter-example generation in formal equivalence verification | Zurab Khasidashvili, Ziyad Hanna | 2007-01-02 |
| 7117465 | Application of the retimed normal form to the formal equivalence verification of abstract RTL descriptions for pipelined designs | Zurab Khasidashvili, Ziyad Hanna | 2006-10-03 |
| 6792581 | Method and apparatus for cut-point frontier selection and for counter-example generation in formal equivalence verification | Zurab Khasidashvili, Ziyad Hanna | 2004-09-14 |
| 6564358 | Method and system for formal verification of a circuit model using binary decision diagrams | Carl Seger, Ziyad Hanna, Daher Kaiss | 2003-05-13 |