Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date | Approx Value ⓘ |
|---|---|---|---|---|
| 8214780 | Optimization of verification of chip design | Tal Erlich, Maayan Fishelson | 2012-07-03 | $15,024,000 |
| 6564358 | Method and system for formal verification of a circuit model using binary decision diagrams | John Moondanos, Carl Seger, Ziyad Hanna | 2003-05-13 | $40,032,000 |