| 11651992 |
Gap fill void and connection structures |
Haigou Huang, Paul Ackmann, Guoxiang Ning |
2023-05-16 |
| 10923388 |
Gap fill void and connection structures |
Haigou Huang, Paul Ackmann, Guoxiang Ning |
2021-02-16 |
| 10777413 |
Interconnects with non-mandrel cuts formed by early block patterning |
Guoxiang Ning, Haigou Huang, Sunil Kumar Singh |
2020-09-15 |
| 10770344 |
Chamferless interconnect vias of semiconductor devices |
Haigou Huang, Ravi Prakash Srivastava, Zhiguo Sun, Qiang Fang, Cheng Xu +1 more |
2020-09-08 |
| 10600914 |
Isolation pillar first gate structures and methods of forming same |
Wei Zhao, Ming Hao Tang, Haiting Wang, Rui Chen, Hui Zang +2 more |
2020-03-24 |
| 10566291 |
Mark structure for aligning layers of integrated circuit structure and methods of forming same |
Ming Hao Tang, Rui Chen, Bradley Morgenfeld, Zheng Chen |
2020-02-18 |
| 10395926 |
Multiple patterning with mandrel cuts formed using a block mask |
Minghao Tang, Sean Xuan Lin, Shao Beng Law, Genevieve Beique, Xun XIANG +1 more |
2019-08-27 |
| 10319626 |
Interconnects with cuts formed by block patterning |
Minghao Tang, Rui Chen |
2019-06-11 |
| 10002827 |
Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC device |
Guoxiang Ning, Chin Teong Lim, Xusheng Wu, Paul Ackmann |
2018-06-19 |
| 9817927 |
Hard mask etch and dielectric etch aware overlap for via and metal layers |
Guo Xiang Ning, David N. Power, Lalit Shokeen, Chin Teong Lim, Paul Ackmann +1 more |
2017-11-14 |
| 9672313 |
Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC device |
Guoxiang Ning, Chin Teong Lim, Xusheng Wu, Paul Ackmann |
2017-06-06 |
| 9666476 |
Dimension-controlled via formation processing |
Xiang Hu, Duohui Bei, Sipeng Gu, Huang Liu |
2017-05-30 |
| 9305832 |
Dimension-controlled via formation processing |
Xiang Hu, Duohui Bei, Sipeng Gu, Huang Liu |
2016-04-05 |
