Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8008200 | Poison-free and low ULK damage integration scheme for damascene interconnects | Ping Jiang, Yong-Seok Choi | 2011-08-30 |
| 7884019 | Poison-free and low ULK damage integration scheme for damascene interconnects | Ping Jiang, Yong-Seok Choi | 2011-02-08 |
| 7425512 | Method for etching a substrate and a device formed using the method | Kezhakkedath R. Udayakumar, Ted S. Moise, Scott R. Summerfelt, Martin G. Albrecht, Francis G. Celii | 2008-09-16 |
| 7192880 | Method for line etch roughness (LER) reduction for low-k interconnect damascene trench etching | — | 2007-03-20 |
| 7087518 | Method of passivating and/or removing contaminants on a low-k dielectric/copper surface | David Gerald Farber, Robert J. Kraft, Andrew John McKerrow, Kenneth Newton, Ting Tsui | 2006-08-08 |
| 7067435 | Method for etch-stop layer etching during damascene dielectric etching with low polymerization | — | 2006-06-27 |
| 6984580 | Dual damascene pattern liner | Robert J. Kraft, Kenneth D. Brennan | 2006-01-10 |
| 5268067 | Wafer clamping method | Lee M. Loewenstein | 1993-12-07 |