Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8479070 | Integrated circuit arrangement for test inputs | Lawrence D. Curley, Ronald J. Frishmuth, Ralf Ludewig, Ching-Lung Tong, Tobias Webel | 2013-07-02 |
| 6816990 | VLSI chip test power reduction | Peilin Song, Timothy J. Koprowski, Franco Motika | 2004-11-09 |
| 6774656 | Self-test for leakage current of driver/receiver stages | Otto A. Torreiter, Joseph Eckelman, David Hui | 2004-08-10 |
| 6728914 | Random path delay testing methodology | Kevin William McCauley, William V. Huott, Mary P. Kusko, Peilin Song, Richard F. Rizzolo +1 more | 2004-04-27 |
| 6725171 | Self-test with split, asymmetric controlled driver output stage | Otto A. Torreiter, Joseph Eckelman, David Hui | 2004-04-20 |
| 6662324 | Global transition scan based AC method | Franco Motika, Richard F. Rizzolo, Peilin Song, William V. Huott | 2003-12-09 |
| 6490702 | Scan structure for improving transition fault coverage and scan diagnostics | Peilin Song, Richard F. Rizzolo, Franco Motika | 2002-12-03 |