Issued Patents All Time
Showing 25 most recent of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9647208 | Low voltage embedded memory having conductive oxide and electrode stacks | Elijah V. Karpov, Brian S. Doyle, Charles C. Kuo, Robert S. Chau, Eric R. Dickey +1 more | 2017-05-09 |
| 9231204 | Low voltage embedded memory having conductive oxide and electrode stacks | Elijah V. Karpov, Brian S. Doyle, Charles C. Kuo, Robert S. Chau, Eric R. Dickey +1 more | 2016-01-05 |
| 8552560 | Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing | Hemanshu Bhatt, Dilip Vijay, Jayanthi Pallinti, Hong Ying, Chiyi Kao | 2013-10-08 |
| 8384165 | Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow | Richard J. Carter, Wai Lo, Hong Lin, Verne Hornback | 2013-02-26 |
| 8076779 | Reduction of macro level stresses in copper/low-K wafers | Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Hong Ying, Chiyi Kao +1 more | 2011-12-13 |
| 7956401 | Bi-axial texturing of high-K dielectric films to reduce leakage currents | Wai Lo, Wilbur G. Catabay | 2011-06-07 |
| 7915122 | Self-aligned cell integration scheme | Richard J. Carter, Hemanshu Bhatt, Shiqun Gu, Peter A. Burke, James R. B. Elmer +2 more | 2011-03-29 |
| 7619272 | Bi-axial texturing of high-K dielectric films to reduce leakage currents | Wai Lo, Wilbur G. Catabay | 2009-11-17 |
| 7582566 | Method for redirecting void diffusion away from vias in an integrated circuit design | Derryl D. J. Allman, Hemanshu Bhatt, Charles E. May, Peter A. Burke, Byung Sung Kwak +2 more | 2009-09-01 |
| 7531442 | Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing | Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Hong Ying, Chiyi Kao +3 more | 2009-05-12 |
| 7436040 | Method and apparatus for diverting void diffusion in integrated circuit conductors | Derryl D. J. Allman, Hemanshu Bhatt, Charles E. May, Peter A. Burke, Byung Sung Kwak +2 more | 2008-10-14 |
| 7405116 | Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow | Richard J. Carter, Wai Lo, Hong Lin, Verne Hornback | 2008-07-29 |
| 7402770 | Nano structure electrode design | Hemanshu Bhatt, Peter A. Burke, Richard J. Carter | 2008-07-22 |
| 7365015 | Damascene replacement metal gate process with controlled gate profile and length using Si1-xGex as sacrificial material | Hong Lin, Wai Lo, Richard J. Carter | 2008-04-29 |
| 7361965 | Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design | Derryl D. J. Allman, Hemanshu Bhatt, Charles E. May, Peter A. Burke, Byung Sung Kwak +2 more | 2008-04-22 |
| 7312127 | Incorporating dopants to enhance the dielectric properties of metal silicates | Wai Lo, Verne Hornback, Wilbur G. Catabay, Wei-Jen Hsia | 2007-12-25 |
| 7300869 | Integrated barrier and seed layer for copper interconnect technology | Byung Sung Kwak, Peter A. Burke | 2007-11-27 |
| 7205673 | Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing | Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Hong Ying, Chiyi Kao | 2007-04-17 |
| 7196420 | Method and structure for creating ultra low resistance damascene copper wiring | Peter A. Burke, Hongqiang Lu | 2007-03-27 |
| 7179736 | Method for fabricating planar semiconductor wafers | Byung Sung Kwak, Peter A. Burke | 2007-02-20 |
| 7064062 | Incorporating dopants to enhance the dielectric properties of metal silicates | Wai Lo, Verne Hornback, Wilbur G. Catabay, Wei-Jen Hsia | 2006-06-20 |
| 7015096 | Bimetallic oxide compositions for gate dielectrics | Vladimir Zubkov | 2006-03-21 |
| 6998343 | Method for creating barrier layers for copper diffusion | Grace Sun, Vladimir Zubkov, William K. Barth, Sethuraman Lakshminarayanan, Agajan Suvkhanov +1 more | 2006-02-14 |
| 6987059 | Method and structure for creating ultra low resistance damascene copper wiring | Peter A. Burke, Hongqiang Lu | 2006-01-17 |
| 6955937 | Carbon nanotube memory cell for integrated circuit structure with removable side spacers to permit access to memory cell and process for forming such memory cell | Peter A. Burke, Hong-Qiang Lu | 2005-10-18 |