Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11687135 | Controlling power delivery to a processor via a bypass | Sanjeev Jahagirdar, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar +3 more | 2023-06-27 |
| 11442103 | Multibit vectored sequential with scan | Amit Agarwal, Ram Krishnamurthy, Steven Hsu, Simeon Realov | 2022-09-13 |
| 11398814 | Low-power single-edge triggered flip-flop, and time borrowing internally stitched flip-flop | Steven Hsu, Amit Agarwal, Simeon Realov, Ram Krishnamurthy | 2022-07-26 |
| 11157052 | Controlling power delivery to a processor via a bypass | Sanjeev Jahagirdar, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar +3 more | 2021-10-26 |
| 11009549 | Multibit vectored sequential with scan | Amit Agarwal, Ram Krishnamurthy, Steven Hsu, Simeon Realov | 2021-05-18 |
| 10473718 | Multibit vectored sequential with scan | Amit Agarwal, Ram Krishnamurthy, Steven Hsu, Simeon Realov | 2019-11-12 |
| 10429913 | Controlling power delivery to a processor via a bypass | Sanjeev Jahagirdar, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar +3 more | 2019-10-01 |
| 10409346 | Controlling power delivery to a processor via a bypass | Sanjeev Jahagirdar, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar +3 more | 2019-09-10 |
| 10146283 | Controlling power delivery to a processor via a bypass | Sanjeev Jahagirdar, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar +3 more | 2018-12-04 |
| 9823719 | Controlling power delivery to a processor via a bypass | Sanjeev Jahagirdar, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar +3 more | 2017-11-21 |
| 9336008 | Shared function multi-ported ROM apparatus and method | Subramaniam Maiyuran | 2016-05-10 |
| 9075741 | Dynamic error handling using parity and redundant rows | Altug Koker, Shailesh Shah, Aditya Navale, Murali Ramadoss | 2015-07-07 |
| 8713256 | Method, apparatus, and system for energy efficiency and energy conservation including dynamic cache sizing and cache operating voltage management for optimal power performance | Inder M. Sodhi, Sanjeev Jahagirdar, Ryan D. Wells | 2014-04-29 |
| 8448010 | Increasing memory bandwidth in processor-based systems | Subramaniam Maiyuran, Anupama Ambardar, Arindrajit Ghosh | 2013-05-21 |
| 8356202 | System and method for reducing power consumption in a device using register files | Scott E. Siers, Omar Malik | 2013-01-15 |
| 8345491 | Memory cell write | Ak R. Ahmed, Scott E. Siers | 2013-01-01 |
| 8050116 | Memory cell write | Ak R. Ahmed, Scott E. Siers | 2011-11-01 |
| 7805619 | Circuit technique to reduce leakage during reduced power mode | John R. Cherukuri, Ak R. Ahmed, Arun Subbiah | 2010-09-28 |
| 7689772 | Power-performance modulation in caches using a smart least recently used scheme | Subramaniam Maiyuran, Truyen Trinh, Parag Raval, Peter J. Smith | 2010-03-30 |
| 7457917 | Reducing power consumption in a sequential cache | Subramaniam Maiyuran, Peter J. Smith, Navin Monteiro | 2008-11-25 |
| 7155574 | Look ahead LRU array update scheme to minimize clobber in sequentially accessed memory | Peter J. Smith, Subramaniam Maiyuran | 2006-12-26 |
| 7136984 | Low power cache architecture | Subramaniam Maiyuran, Lyman Moulton, Salvador Palanca | 2006-11-14 |
| 7130236 | Low power delay controlled zero sensitive sense amplifier | Iqbal Rajwani | 2006-10-31 |