Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7136984 | Low power cache architecture | Subramaniam Maiyuran, Salvador Palanca, Satish K. Damaraju | 2006-11-14 |
| 6845432 | Low power cache architecture | Subramaniam Maiyuran | 2005-01-18 |
| 5644744 | Superscaler instruction pipeline having boundary identification logic for variable length instructions | Stephen W. Mahin, Stephen M. Conor, Stephen J. Ciavaglia, Stephen E. Rich, Paul D. Kartschoke | 1997-07-01 |
| 5640526 | Superscaler instruction pipeline having boundary indentification logic for variable length instructions | Stephen W. Mahin, Stephen M. Conor, Stephen J. Ciavaglia, Stephen E. Rich, Paul D. Kartschoke | 1997-06-17 |
| 5625787 | Superscalar instruction pipeline using alignment logic responsive to boundary identification logic for aligning and appending variable length instructions to instructions stored in cache | Stephen W. Mahin, Stephen M. Conor, Stephen J. Ciavaglia, Stephen E. Rich, Paul D. Kartschoke | 1997-04-29 |