Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7222268 | System resource availability manager | Arthur L. Zaifman | 2007-05-22 |
| 6397306 | Per memory atomic access for distributed memory multiprocessor architecture | Arthur L. Zaifman, Edward C. Szajner, Jr., Edward Spang | 2002-05-28 |
| 6292826 | Shadow arrays for distributed memory multiprocessor architecture | Arthur L. Zaifman, Edward C. Szajner, Jr. | 2001-09-18 |
| 5884061 | Apparatus to perform source operand dependency analysis perform register renaming and provide rapid pipeline recovery for a microprocessor capable of issuing and executing multiple instructions out-of-order in a single processor cycle | James H. Hesson, Jay LeBlanc, Walter Thomas Esling, Pamela A. Wilcox | 1999-03-16 |
| 5666506 | Apparatus to dynamically control the out-of-order execution of load/store instructions in a processor capable of dispatchng, issuing and executing multiple instructions in a single processor cycle | James H. Hesson, Jay LeBlanc | 1997-09-09 |
| 5644744 | Superscaler instruction pipeline having boundary identification logic for variable length instructions | Stephen W. Mahin, Stephen M. Conor, Lyman Moulton, Stephen E. Rich, Paul D. Kartschoke | 1997-07-01 |
| 5640526 | Superscaler instruction pipeline having boundary indentification logic for variable length instructions | Stephen W. Mahin, Stephen M. Conor, Lyman Moulton, Stephen E. Rich, Paul D. Kartschoke | 1997-06-17 |
| 5625789 | Apparatus for source operand dependendency analyses register renaming and rapid pipeline recovery in a microprocessor that issues and executes multiple instructions out-of-order in a single cycle | James H. Hesson, Jay LeBlanc, Walter Thomas Esling, Pamela A. Wilcox | 1997-04-29 |
| 5625787 | Superscalar instruction pipeline using alignment logic responsive to boundary identification logic for aligning and appending variable length instructions to instructions stored in cache | Stephen W. Mahin, Stephen M. Conor, Lyman Moulton, Stephen E. Rich, Paul D. Kartschoke | 1997-04-29 |
| 5615350 | Apparatus to dynamically control the out-of-order execution of load-store instructions in a processor capable of dispatching, issuing and executing multiple instructions in a single processor cycle | James H. Hesson, Jay LeBlanc | 1997-03-25 |
| 5193157 | Piplined system includes a selector for loading condition code either from first or second condition code registers to program counter | Russell G. Barbour, Carl A. Soeder | 1993-03-09 |
| 5175829 | Method and apparatus for bus lock during atomic computer operations | Bernard L. Stumpf, George M. Stabler, Richard G. Bahr, Barry J. Flahive, Hugh C. Lauer | 1992-12-29 |
| 5051885 | Data processing system for concurrent dispatch of instructions to multiple functional units | John S. Yates, Jr., John C. Manton, Michael Kahaiyan, Richard G. Bahr, Barry J. Flahive | 1991-09-24 |
| 5045992 | Apparatus for executing instruction regardless of data types and thereafter selectively branching to other instruction upon determining of incompatible data type | John S. Yates, Jr. | 1991-09-03 |