Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11687135 | Controlling power delivery to a processor via a bypass | Sanjeev Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi +3 more | 2023-06-27 |
| 11157052 | Controlling power delivery to a processor via a bypass | Sanjeev Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi +3 more | 2021-10-26 |
| 10429913 | Controlling power delivery to a processor via a bypass | Sanjeev Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi +3 more | 2019-10-01 |
| 10409346 | Controlling power delivery to a processor via a bypass | Sanjeev Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi +3 more | 2019-09-10 |
| 10146283 | Controlling power delivery to a processor via a bypass | Sanjeev Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi +3 more | 2018-12-04 |
| 9823719 | Controlling power delivery to a processor via a bypass | Sanjeev Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi +3 more | 2017-11-21 |
| 9698781 | Dynamic clock gating frequency scaling | Arojit Roychowdhury, Ajaya V. Durg, Shilpa Huddar, Sunil Shanbhag, Tejpal Singh | 2017-07-04 |
| 9223365 | Method and apparatus for controlled reset sequences without parallel fuses and PLL'S | Ivan Herrera Mejia, Vijay K. Vuppaladadium | 2015-12-29 |
| 7668948 | Staggered time zones | Ajith Prasad, Simon Luigi Sabato | 2010-02-23 |