Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12210477 | Systems and methods for improving cache efficiency and utilization | Altug Koker, Joydeep Ray, Ben J. Ashbaugh, Jonathan Pearce, Abhishek R. Appu +19 more | 2025-01-28 |
| 11620256 | Systems and methods for improving cache efficiency and utilization | Altug Koker, Joydeep Ray, Ben J. Ashbaugh, Jonathan Pearce, Abhishek R. Appu +19 more | 2023-04-04 |
| 9075741 | Dynamic error handling using parity and redundant rows | Altug Koker, Aditya Navale, Murali Ramadoss, Satish K. Damaraju | 2015-07-07 |
| 7221200 | Programmable low voltage reset apparatus for multi-Vdd chips | Prasad Rao Kotra, Sunil Thamaran | 2007-05-22 |
| 7170179 | Chip select method through double bonding | — | 2007-01-30 |
| 6822899 | Method of protecting flash memory from data corruption during fast power down events | Khaled Boulos, Carlos Awong | 2004-11-23 |
| 6523055 | Circuit and method for multiplying and accumulating the sum of two products in a single cycle | Robert K. Yu, Satish Padmanabhan, Chakra R. Srivatsa | 2003-02-18 |
| 6222393 | Apparatus and method for generating a pulse signal | Gregory J. Landry | 2001-04-24 |
| 5987603 | Apparatus and method for reversing bits using a shifter | — | 1999-11-16 |
| 5933032 | Apparatus and method for generating a pulse signal | Gregory J. Landry | 1999-08-03 |
| 5903174 | Method and apparatus for reducing skew among input signals within an integrated circuit | Greg J. Landry, Ashish Pancholy | 1999-05-11 |
| 5835970 | Burst address generator having two modes of operation employing a linear/nonlinear counter using decoded addresses | Greg J. Landry | 1998-11-10 |
| 5835401 | Dram with hidden refresh | Gary Green, John Q. Torode, T. J. Rodgers | 1998-11-10 |
| 5652732 | Apparatus and method for matching a clock delay to a delay through a memory array | — | 1997-07-29 |
| 5559465 | Output preconditioning circuit with an output level latch and a clamp | — | 1996-09-24 |
| 5490115 | Method and apparatus for writing to memory cells in a minimum number of cycles during a memory test operation | Gregory J. Landry | 1996-02-06 |