GL

Greg J. Landry

Cypress Semiconductor: 20 patents #75 of 1,852Top 5%
EN Extreme Networks: 2 patents #118 of 403Top 30%
PT Parade Technologies: 2 patents #54 of 165Top 35%
AV Avaya: 1 patents #821 of 1,730Top 50%
Overall (All Time): #163,555 of 4,157,543Top 4%
25
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10193748 Enabling configuration in networks Zenon Kuc, Roger Lapuh, Karthik Gopalakrishnan, Paul Unbehagen, John P. Mead 2019-01-29
9954764 Performing MAC-in-MAC encapsulation using shortest path bridging configuration information Zenon Kuc, Roger Lapuh, Karthik Gopalakrishnan, Paul Unbehagen, John P. Mead 2018-04-24
9459736 Flexible capacitive sensor array Massoud Badaye 2016-10-04
9454268 Force sensing capacitive hybrid touch sensor Massoud Badaye 2016-09-27
9191233 Message transmission in networks Zenon Kuc, Roger Lapuh, Karthik Gopalakrishnan, Paul Unbehagen, John P. Mead 2015-11-17
8903679 Accuracy in a capacitive sense array Tao Peng 2014-12-02
8692799 Single layer multi-touch capacitive sensor Steve Kolokowsky, David G. Wright 2014-04-08
7777521 Method and circuitry to translate a differential logic signal to a CMOS logic signal Sherif Hanna, Alan ReFalo, Jeyenth Vijayaraghavan 2010-08-17
7616513 Memory device, current sense amplifier, and method of operating the same Tao Peng 2009-11-10
7301370 High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion Sherif Hanna, Alan ReFalo, Jeyenth Vijayaraghavan 2007-11-27
7230856 High-speed multiplexer latch Rajesh Venugopal, Tao Peng 2007-06-12
7126398 Method and an apparatus to generate static logic level output Eric H. Voelkel, Robert M. Reinschmidt 2006-10-24
6611935 Method and system for efficiently testing circuitry 2003-08-26
6563437 Method and apparatus for using programmable logic device (PLD) logic for decompression of configuration data Timothy M. Lacey 2003-05-13
6507932 METHODS OF CONVERTING AND/OR TRANSLATING A LAYOUT OR CIRCUIT SCHEMATIC OR NETLIST THEREOF TO A SIMULATION SCHEMATIC OR NETLIST, AND/OR OF SIMULATING FUNCTION(S) AND/OR PERFORMANCE CHARACTERISTIC(S) OF A CIRCUIT Alan R. Hawse 2003-01-14
6486712 Programmable switch Robert M. Reinschmidt, Timothy M. Lacey 2002-11-26
6466505 Flexible input structure for an embedded memory 2002-10-15
6411140 Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit 2002-06-25
6333891 Circuit and method for controlling a wordline and/or stabilizing a memory cell Peter Adamek 2001-12-25
6298005 Configurable memory block 2001-10-02
6134181 Configurable memory block 2000-10-17
6088289 Circuit and method for controlling a wordline and/or stabilizing a memory cell Peter Adamek 2000-07-11
6043684 Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit 2000-03-28
5903174 Method and apparatus for reducing skew among input signals within an integrated circuit Shailesh Shah, Ashish Pancholy 1999-05-11
5835970 Burst address generator having two modes of operation employing a linear/nonlinear counter using decoded addresses Shailesh Shah 1998-11-10