Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8877161 | GM1-like peptides and uses thereof | Han-Chung Wu | 2014-11-04 |
| 8513197 | Ganglioside epitopes for treating Guillain-Barre syndrome | Seigo Usuki | 2013-08-20 |
| 8236765 | Ganglioside epitopes for treating guillain-barre syndrome | Seigo Usuki | 2012-08-07 |
| 6523055 | Circuit and method for multiplying and accumulating the sum of two products in a single cycle | Satish Padmanabhan, Chakra R. Srivatsa, Shailesh Shah | 2003-02-18 |
| 6436687 | cDNA sequence of mouse brain sialidase gene | Chris Fronda, Guichao Zeng | 2002-08-20 |
| 6410597 | Hydroxyalkyl amide analogs of ceramide | Erhard Bieberich, Raphael Ottenbrite, Helen Fillmore, William C. Broaddus | 2002-06-25 |
| 6280989 | Sialyltransferases | Dmitri Kapitonov | 2001-08-28 |
| 5987638 | Apparatus and method for computing the result of a viterbi equation in a single cycle | Satish Padmanabhan | 1999-11-16 |
| 5954789 | Quotient digit selection logic for floating point division/square root | Nasima Parveen, J. Arjun Prabhu | 1999-09-21 |
| 5872717 | Apparatus and method for verifying the timing performance of critical paths within a circuit using a static timing analyzer and a dynamic timing analyzer | Paul Yip, Manjunath Doreswamy | 1999-02-16 |
| 5790446 | Floating point multiplier with reduced critical paths using delay matching techniques | Gregory B. Zyner | 1998-08-04 |
| 5671171 | Shared rounding hardware for multiplier and divider/square root unit using conditional sum adder | Grzegorz B. Zyner | 1997-09-23 |
| 5619439 | Shared hardware for multiply, divide, and square root exponent calculation | Grzegorz B. Zyner | 1997-04-08 |
| 5602769 | Method and apparatus for partially supporting subnormal operands in floating point multiplication | Grzegorz B. Zyner | 1997-02-11 |