Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Robert K. Yu — 14 Patents

Oracle: 6 patents #2,079 of 14,854Top 15%
VUVirginia Commonwealth University: 2 patents #119 of 594Top 25%
LSLsi: 2 patents #1,474 of 3,238Top 50%
GIGeorgia Regents Research Institute: 1 patents #1 of 21Top 5%
MIMedical College Of Georgia Research Institute: 1 patents #21 of 68Top 35%
Newark, CA: #113 of 939 inventorsTop 15%
California: #43,920 of 386,348 inventorsTop 15%
Overall (All Time): #332,869 of 4,157,543Top 9%
14 Patents All Time
Robert K. Yu has been granted 14 US patents while listed as an inventor at Oracle. The first was granted in 1997 and the most recent in November 2014. Robert K. Yu ranks #332,869 of 4,157,543 US inventors in our database (top 8.0%). Patent records list Robert K. Yu in Newark, CA, US.

Issued Patents All Time

Showing 1–14 of 14 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8877161 GM1-like peptides and uses thereof Han-Chung Wu 2014-11-04
8513197 Ganglioside epitopes for treating Guillain-Barre syndrome Seigo Usuki 2013-08-20
8236765 Ganglioside epitopes for treating guillain-barre syndrome Seigo Usuki 2012-08-07
6523055 Circuit and method for multiplying and accumulating the sum of two products in a single cycle Satish Padmanabhan, Chakra R. Srivatsa, Shailesh Shah 2003-02-18 $6,683,000
6436687 cDNA sequence of mouse brain sialidase gene Chris Fronda, Guichao Zeng 2002-08-20
6410597 Hydroxyalkyl amide analogs of ceramide Erhard Bieberich, Raphael Ottenbrite, Helen Fillmore, William C. Broaddus 2002-06-25
6280989 Sialyltransferases Dmitri Kapitonov 2001-08-28
5987638 Apparatus and method for computing the result of a viterbi equation in a single cycle Satish Padmanabhan 1999-11-16 $14,390,000
5954789 Quotient digit selection logic for floating point division/square root Nasima Parveen, J. Arjun Prabhu 1999-09-21 $84,680,000
5872717 Apparatus and method for verifying the timing performance of critical paths within a circuit using a static timing analyzer and a dynamic timing analyzer Paul Yip, Manjunath Doreswamy 1999-02-16 $42,785,000
5790446 Floating point multiplier with reduced critical paths using delay matching techniques Gregory B. Zyner 1998-08-04 $14,202,000
5671171 Shared rounding hardware for multiplier and divider/square root unit using conditional sum adder Grzegorz B. Zyner 1997-09-23 $60,729,000
5619439 Shared hardware for multiply, divide, and square root exponent calculation Grzegorz B. Zyner 1997-04-08 $36,894,000
5602769 Method and apparatus for partially supporting subnormal operands in floating point multiplication Grzegorz B. Zyner 1997-02-11 $63,518,000