Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Floating point multiplier with reduced critical paths using delay matching techniques

Floating point multiplier with reduced critical paths using delay matching techniques

US Patent 5790446 · Granted Aug 4, 1998

Estimated economic value: $14,202,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

GM1-like peptides and uses thereof2014
Ganglioside epitopes for treating Guillain-Barre syndrome2013
Ganglioside epitopes for treating guillain-barre syndrome2012
Circuit and method for multiplying and accumulating the sum of two products in a2003
cDNA sequence of mouse brain sialidase gene2002
Hydroxyalkyl amide analogs of ceramide2002
Sialyltransferases2001
Apparatus and method for computing the result of a viterbi equation in a single 1999
Quotient digit selection logic for floating point division/square root1999
Apparatus and method for verifying the timing performance of critical paths with1999
Shared rounding hardware for multiplier and divider/square root unit using condi1997
Shared hardware for multiply, divide, and square root exponent calculation1997