Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6727569 | Method of making enhanced trench oxide with low temperature nitrogen integration | Mark I. Gardner, Mark C. Gilmer | 2004-04-27 |
| 6309936 | Integrated formation of LDD and non-LDD semiconductor devices | Mark I. Gardner, Thomas E. Spikes, Jr. | 2001-10-30 |
| 6214123 | Chemical vapor deposition systems and methods for depositing films on semiconductor wafers | Mark I. Gardner, Mark C. Gilmer | 2001-04-10 |
| 6194283 | High density trench fill due to new spacer fill method including isotropically etching silicon nitride spacers | Mark I. Gardner, Thomas E. Spikes, Jr. | 2001-02-27 |
| 6160316 | Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths | Mark I. Gardner, Thomas E. Spikes, Jr. | 2000-12-12 |
| 6148832 | Method and apparatus for in-situ cleaning of polysilicon-coated quartz furnaces | Mark C. Gilmer, Mark I. Gardner | 2000-11-21 |
| 6140191 | Method of making high performance MOSFET with integrated simultaneous formation of source/drain and gate regions | Mark I. Gardner, Mark C. Gilmer | 2000-10-31 |
| 6051487 | Semiconductor device fabrication using a sacrificial plug for defining a region for a gate electrode | Mark I. Gardner, H. Jim Fulford, Mark C. Gilmer | 2000-04-18 |
| 6043533 | Method of integrating Ldd implantation for CMOS device fabrication | Mark I. Gardner, Fred N. Hause | 2000-03-28 |
| 6037244 | Method of manufacturing a semiconductor device using advanced contact formation | Mark I. Gardner, Thomas E. Spikes, Jr., Frederick N. Hause, Sey-Ping Sun | 2000-03-14 |
| 5970350 | Semiconductor device having a thin gate oxide and method of manufacture thereof | Mark I. Gardner, Thomas, Jr. E. Spikes | 1999-10-19 |
| 5946581 | Method of manufacturing a semiconductor device by doping an active region after formation of a relatively thick oxide layer | Mark I. Gardner, Thomas E. Spikes, Jr. | 1999-08-31 |
| 5942787 | Small gate electrode MOSFET | Mark I. Gardner, Thomas E. Spikes, Jr. | 1999-08-24 |
| 5929496 | Method and structure for channel length reduction in insulated gate field effect transistors | Mark I. Gardner, Thomas E. Spikes, Jr. | 1999-07-27 |
| 5918133 | Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof | Mark I. Gardner | 1999-06-29 |
| 5863818 | Multilevel transistor fabrication method having an inverted, upper level transistor | Daniel Kadosh, Mark I. Garnder | 1999-01-26 |
| 5851307 | Method for in-situ cleaning of polysilicon-coated quartz furnaces | Mark C. Gilmer, Mark I. Gardner | 1998-12-22 |