Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10956349 | Support for multiple widths of DRAM in double data rate controllers or data buffers | Alejandro F. Gonzalez, Craig DeSimone, Garret Davey, Yue Yu, Scott Herrington | 2021-03-23 |
| 10565144 | Double data rate controllers and data buffers with support for multiple data widths of DRAM | Alejandro F. Gonzalez, Craig DeSimone, Garret Davey, Yue Yu, Scott Herrington | 2020-02-18 |
| 9793708 | Overvoltage protection circuits and methods of operating same | Alan Glaser, Tak Kwong Wong, Al Xuefeng Fang, Jon R. Williamson | 2017-10-17 |
| 7196562 | Programmable clock drivers that support CRC error checking of configuration data during program restore operations | Bradley C. Luis, Srinivas Satish Babu Bamdhamravuri | 2007-03-27 |
| 7151398 | Clock signal generators having programmable full-period clock skew control | Shawn Giguere, Declan McDonagh, Bamdhamravuri S. Satishbabu | 2006-12-19 |
| 7120075 | Multi-FIFO integrated circuit devices that support multi-queue operating modes with enhanced write path and read path queue switching | David Gibson | 2006-10-10 |
| 7082071 | Integrated DDR/SDR flow control managers that support multiple queues and MUX, DEMUX and broadcast operating modes | David Gibson, Mario Montana, Mario Au, Stewart Speed, Srinivas Satish Babu Bamdhamravuri +1 more | 2006-07-25 |
| 7079446 | DRAM interface circuits having enhanced skew, slew rate and impedance control | Paul Murtagh | 2006-07-18 |
| 6977539 | Clock signal generators having programmable full-period clock skew control and methods of generating clock signals having programmable skews | Declan McDonagh | 2005-12-20 |
| 6510486 | Clocking scheme for independently reading and writing multiple width words from a memory array | Andrew L. Hawkins | 2003-01-21 |
| 6173425 | Methods of testing integrated circuits to include data traversal path identification information and related status information in test data streams | Bruce Lorenz Chin | 2001-01-09 |
| 6023777 | Testing method for devices with status flags | — | 2000-02-08 |
| 6005821 | Circuit and method for instruction controllable slew rate of bit line driver | Shiva P. Gowni | 1999-12-21 |
| 5978307 | Integrated circuit memory devices having partitioned multi-port memory arrays therein for increasing data bandwidth and methods of operating same | Robert J. Proebsting | 1999-11-02 |
| 5968190 | Redundancy method and circuit for self-repairing memory arrays | — | 1999-10-19 |
| 5898315 | Output buffer circuit and method having improved access | — | 1999-04-27 |
| 5872802 | Parity generation and check circuit and method in read data path | Brian P. Evans | 1999-02-16 |
| 5852748 | Programmable read-write word line equality signal generation for FIFOs | Andrew L. Hawkins, Pidugu L. Narayana | 1998-12-22 |
| 5828617 | Multiple word width memory array clocking scheme for reading words from a memory array | — | 1998-10-27 |
| 5812465 | Redundancy circuit and method for providing word lines driven by a shift register | Cameron Lacy, Brendon Lewis Johnson | 1998-09-22 |
| 5777944 | Circuit and method for instruction controllable slewrate of bit line driver | Shiva P. Gowni | 1998-07-07 |
| 5764967 | Multiple frequency memory array clocking scheme for reading and writing multiple width digital words | — | 1998-06-09 |
| 5712820 | Multiple word width memory array clocking scheme | — | 1998-01-27 |
| 5682356 | Multiple word width memory array clocking scheme for reading words from a memory array | — | 1997-10-28 |
| 5642318 | Testing method for FIFOS | Andrew L. Hawkins, Richard A Rodell, Jr. | 1997-06-24 |