Issued Patents All Time
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6907539 | Configurage data setup/hold timing circuit with user programmable delay | Padma S. Nagarasa, Beng-Ghee Teh | 2005-06-14 |
| 6675336 | Distributed test architecture for multiport RAMs or other circuitry | Sangeeta Thakur, Emad Hamadeh | 2004-01-06 |
| 6628171 | Method, architecture and circuit for controlling and/or operating an oscillator | Richard K. Chou, Paul H. Scott | 2003-09-30 |
| 6577635 | Data packet transmission scheduling | Makarand Dharmapurikar | 2003-06-10 |
| 6526470 | Fifo bus-sizing, bus-matching datapath architecture | Daniel Eric Cress, Sangeeta Thakur | 2003-02-25 |
| 6489805 | Circuits, architectures, and methods for generating a periodic signal in a memory | Johnie Au, Sangeeta Thakur | 2002-12-03 |
| 6469983 | Data packet transmission scheduling using a partitioned heap | Makarand Dharmapurikar | 2002-10-22 |
| 6400642 | Memory architecture | Rakesh Mehrotra | 2002-06-04 |
| 6377071 | Composite flag generation for DDR FIFOs | Bo Wang | 2002-04-23 |
| 6366979 | Apparatus and method for shorting retransmit recovery times utilizing cache memory in high speed FIFO | Daniel Eric Cress, Ping Wu | 2002-04-02 |
| 6292013 | Column redundancy scheme for bus-matching fifos | Daniel Eric Cress, Derrick J. Savage | 2001-09-18 |
| 6240031 | Memory architecture | Rakesh Mehrotra | 2001-05-29 |
| 6177843 | Oscillator circuit controlled by programmable logic | Richard K. Chou, Paul H. Scott | 2001-01-23 |
| 6070203 | Circuit for generating almost full and almost empty flags in response to sum and carry outputs in asynchronous and synchronous FIFOS | Andrew L. Hawkins | 2000-05-30 |
| 6055177 | Memory cell | Daniel Eric Cress, Andrew L. Hawkins, Derrick J. Savage | 2000-04-25 |
| 6023435 | Staggered bitline precharge scheme | Daniel Eric Cress, Andrew L. Hawkins | 2000-02-08 |
| 6016403 | State machine design for generating empty and full flags in an asynchronous FIFO | Andrew L. Hawkins | 2000-01-18 |
| 5994920 | Half-full flag generator for synchronous FIFOs | Andrew L. Hawkins | 1999-11-30 |
| 5991834 | State machine design for generating half-full and half-empty flags in an asynchronous FIFO | Andrew L. Hawkins | 1999-11-23 |
| 5963056 | Full and empty flag generator for synchronous FIFOs | Andrew L. Hawkins | 1999-10-05 |
| 5955897 | Signal generation decoder circuit and method | Andrew L. Hawkins | 1999-09-21 |
| 5860160 | High speed FIFO mark and retransmit scheme using latches and precharge | Daniel Eric Cress, Andrew L. Hawkins, Ping Wu | 1999-01-12 |
| 5852748 | Programmable read-write word line equality signal generation for FIFOs | Andrew L. Hawkins, Roland T. Knaack | 1998-12-22 |
| 5850568 | Circuit having plurality of carry/sum adders having read count, write count, and offset inputs to generate an output flag in response to FIFO fullness | Andrew L. Hawkins | 1998-12-15 |
| 5844423 | Half-full flag generator for synchronous FIFOs | Andrew L. Hawkins | 1998-12-01 |