Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12061846 | Simulation and validation of autonomous vehicle system and components | Chad Partridge, Michael Savchenko, Daniel Schambach | 2024-08-13 |
| 10693686 | DFE open loop training for DDR data buffer and registered clock driver | Xudong Shi | 2020-06-23 |
| 8381081 | Data loss protection switch system and method | Palani Subbiah | 2013-02-19 |
| 8094562 | Transmission of a continuous datastream through a re-clocked frame-based transport network | Jason Baumbach, Somnath Paul | 2012-01-10 |
| 7979752 | Data loss protection switch system and method | Palani Subbiah | 2011-07-12 |
| 7936854 | Method and system of cycle slip framing in a deserializer | Sean C. Foley, Cazel Lombaard, Tony Blake, Mohamed Sardi | 2011-05-03 |
| 7409616 | Built in self test system and method for detecting and correcting cycle slip within a deserializer | Mohamed Sardi | 2008-08-05 |
| 7372928 | Method and system of cycle slip framing in a deserializer | Sean C. Foley, Carel J. Lombaard, Tony Blake, Mohamed Sardi | 2008-05-13 |
| 7349515 | Method and an apparatus to improve production yield of phase locked loops | Chwei-Po Chew | 2008-03-25 |
| 7151418 | Method and an apparatus to bias a charge pump in a phase locked loop to compensate a VCO gain | Chwei-Po Chew | 2006-12-19 |
| 6970115 | Cycle slip framing system and method for selectively increasing a frame clock cycle to maintain related bits within the same parallel-output frame of a deserializer | Mohamed Sardi, Sean C. Foley | 2005-11-29 |
| 6917661 | Method, architecture and circuitry for controlling pulse width in a phase and/or frequency detector | S. Babar Raza | 2005-07-12 |
| 6886126 | Apparatus and protocol for detected error propagation in serial-transport block-coded interfaces | Edward L. Grivna | 2005-04-26 |
| 6628171 | Method, architecture and circuit for controlling and/or operating an oscillator | Richard K. Chou, Pidugu L. Narayana | 2003-09-30 |
| 6373302 | Phase alignment system | Gabriel Li | 2002-04-16 |
| 6351168 | Phase alignment system | Gabriel Li | 2002-02-26 |
| 6177843 | Oscillator circuit controlled by programmable logic | Richard K. Chou, Pidugu L. Narayana | 2001-01-23 |
| 6084479 | Circuit, architecture and method(s) of controlling a periodic signal generating circuit or device | Michael L. Duffy | 2000-07-04 |
| 6028844 | ATM receiver | Yi-Hsien Hao | 2000-02-22 |
| 5952888 | Roving range control to limit receive PLL frequency of operation | — | 1999-09-14 |
| 5949799 | Minimum-latency data mover with auto-segmentation and reassembly | Edward L. Grivna | 1999-09-07 |
| 5745011 | Data recovery phase locked loop | — | 1998-04-28 |
| 5355097 | Potentiometric oscillator with reset and test input | Bertrand J. Williams | 1994-10-11 |
| 5298810 | BiCMOS CMOS/ECL data multiplexer | Bertrand J. Williams | 1994-03-29 |
| 5079770 | Apparatus and associated methods for converting serial data pattern signals transmitted or suitable for transmission over a high speed synchronous serial transmission media, to parallel pattern output signals | — | 1992-01-07 |