Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6526470 | Fifo bus-sizing, bus-matching datapath architecture | Pidugu L. Narayana, Sangeeta Thakur | 2003-02-25 |
| 6483386 | Low voltage differential amplifier with high voltage protection | Jeffery Scott Hunt | 2002-11-19 |
| 6473357 | Bitline/dataline short scheme to improve fall-through timing in a multi-port memory | Junfei Fan, Jeffery Scott Hunt | 2002-10-29 |
| 6442657 | Flag generation scheme for FIFOs | Junfei Fan | 2002-08-27 |
| 6366979 | Apparatus and method for shorting retransmit recovery times utilizing cache memory in high speed FIFO | Pidugu L. Narayana, Ping Wu | 2002-04-02 |
| 6292013 | Column redundancy scheme for bus-matching fifos | Derrick J. Savage, Pidugu L. Narayana | 2001-09-18 |
| 6191636 | Input buffer/level shifter | Jeffery Scott Hunt, Muthu Nagarajan | 2001-02-20 |
| 6055177 | Memory cell | Pidugu L. Narayana, Andrew L. Hawkins, Derrick J. Savage | 2000-04-25 |
| 6023435 | Staggered bitline precharge scheme | Pidugu L. Narayana, Andrew L. Hawkins | 2000-02-08 |
| 5860160 | High speed FIFO mark and retransmit scheme using latches and precharge | Pidugu L. Narayana, Andrew L. Hawkins, Ping Wu | 1999-01-12 |