Issued Patents All Time
Showing 25 most recent of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11792264 | Multiple sensor data processor interface and relay | Gary Butler, Derrick J. Savage, David Lindley, Muthukumar Nagarajan | 2023-10-17 |
| 10250690 | Multiple sensor data processor interface and relay | Gary Butler, Derrick J. Savage, David Lindley, Muthukumar Nagarajan | 2019-04-02 |
| 9596091 | Multiple sensor data processor interface and relay | Gary Butler, Derrick J. Savage, David Lindley, Muthukumar Nagarajan | 2017-03-14 |
| 8271810 | Method and apparatus for dynamically detecting environmental conditions and adjusting drive strength in response to the detecting | Michael Fliesler, David Lindley, Morgan Whately, Vinod Rajan, Muthukumar Nagarajan +1 more | 2012-09-18 |
| 7808275 | Input buffer with adaptive trip point | George M. Ansel, Anand Chamakura | 2010-10-05 |
| 7479800 | Variable impedance sense architecture and method | Kalyana C. Vullaganti | 2009-01-20 |
| 7139292 | Configurable matrix architecture | Brian P. Evans | 2006-11-21 |
| 7132854 | Data path configurable for multiple clocking arrangements | Suwei Chen, Sanjay Sancheti | 2006-11-07 |
| 7113445 | Multi-port memory cell and access method | Sanjay Sancheti, George M. Ansel | 2006-09-26 |
| 6904436 | Method and system for generating a bit order data structure of configuration bits from a schematic hierarchy | James Daniel Merchant, Gordon Carskadon, Brian P. Evans, Anup Nayak, Andrew Wright | 2005-06-07 |
| 6815984 | Push/pull multiplexer bit | Benjamin J. Bowers, Brian P. Evans | 2004-11-09 |
| 6801064 | Buffer circuit using low voltage transistors and level shifters | Scott A. Jackson | 2004-10-05 |
| 6784717 | Input buffer system using low voltage transistors | Scott A. Jackson | 2004-08-31 |
| 6609243 | Layout architecture to optimize path delays | Brian P. Evans | 2003-08-19 |
| 6532524 | Port prioritization scheme | Junfei Fan | 2003-03-11 |
| 6490712 | Method and system for identifying configuration circuit addresses in a schematic hierarchy | James Daniel Merchant, Gordon Carskadon, Brian P. Evans, Anup Nayak, Andrew Wright | 2002-12-03 |
| 6483386 | Low voltage differential amplifier with high voltage protection | Daniel Eric Cress | 2002-11-19 |
| 6473357 | Bitline/dataline short scheme to improve fall-through timing in a multi-port memory | Junfei Fan, Daniel Eric Cress | 2002-10-29 |
| 6388469 | Multiple power supply output driver | Muthukumar Nagarajan | 2002-05-14 |
| 6353336 | Electrical ID method for output driver | David Lindley, William G. Baker | 2002-03-05 |
| 6191636 | Input buffer/level shifter | Daniel Eric Cress, Muthu Nagarajan | 2001-02-20 |
| 6122203 | Method, architecture and circuit for writing to and reading from a memory during a single cycle | Sudhaker Reddy Anumula, Ajay Srikrishna, Jeffrey W. Waldrip, Satish C. Saripella | 2000-09-19 |
| 6087858 | Self-timed sense amplifier evaluation scheme | Satish C. Saripella | 2000-07-11 |
| 6016277 | Reference voltage generator for reading a ROM cell in an integrated RAM/ROM memory device | George M. Ansel, Satish C. Saripella, Sudhaker Reddy Anumula, Ajay Srikrishna | 2000-01-18 |
| 5986970 | Method, architecture and circuit for writing to a memory | Sudhaker Reddy Anumula, Ajay Srikrishna, Jeffrey W. Waldrip, Satish C. Saripella | 1999-11-16 |