Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6813741 | Address counter test mode for memory device | George M. Ansel, David Lindley, Jeffrey W. Gossett, Junfei Fan, Michael Carlson | 2004-11-02 |
| 6731566 | Single ended simplex dual port memory cell | Stefan P. Sywyk, Richard K. Chou | 2004-05-04 |
| 6510486 | Clocking scheme for independently reading and writing multiple width words from a memory array | Roland T. Knaack | 2003-01-21 |
| 6262912 | Single ended simplex dual port memory cell | Stefan P. Sywyk, Richard K. Chou | 2001-07-17 |
| 6181595 | Single ended dual port memory cell | Stefan P. Sywyk | 2001-01-30 |
| 6078637 | Address counter test mode for memory device | George M. Ansel, David Lindley, Jeffrey W. Gossett, Junfei Fan, Michael Carlson | 2000-06-20 |
| 6070203 | Circuit for generating almost full and almost empty flags in response to sum and carry outputs in asynchronous and synchronous FIFOS | Pidugu L. Narayana | 2000-05-30 |
| 6055177 | Memory cell | Pidugu L. Narayana, Daniel Eric Cress, Derrick J. Savage | 2000-04-25 |
| 6023435 | Staggered bitline precharge scheme | Pidugu L. Narayana, Daniel Eric Cress | 2000-02-08 |
| 6016403 | State machine design for generating empty and full flags in an asynchronous FIFO | Pidugu L. Narayana | 2000-01-18 |
| 6005796 | Single ended simpler dual port memory cell | Stefan P. Sywyk, Richard K. Chou | 1999-12-21 |
| 6005795 | Single ended dual port memory cell | Stefan P. Sywyk | 1999-12-21 |
| 5994920 | Half-full flag generator for synchronous FIFOs | Pidugu L. Narayana | 1999-11-30 |
| 5991834 | State machine design for generating half-full and half-empty flags in an asynchronous FIFO | Pidugu L. Narayana | 1999-11-23 |
| 5963056 | Full and empty flag generator for synchronous FIFOs | Pidugu L. Narayana | 1999-10-05 |
| 5955897 | Signal generation decoder circuit and method | Pidugu L. Narayana | 1999-09-21 |
| 5936894 | Dual level wordline clamp for reduced memory cell current | Jeffery Scott Hunt, Satish C. Saripella, Sanjay Sunder | 1999-08-10 |
| 5880997 | Bubbleback for FIFOS | Muthukumar Nagarajan, Ajay Srikrishna | 1999-03-09 |
| 5864507 | Dual level wordline clamp for reduced memory cell current | Jeffery Scott Hunt, Satish C. Saripella, Sanjay Sunder | 1999-01-26 |
| 5862092 | Read bitline writer for fallthru in fifos | Muthukumar Nagarajan, Ajay Srikrishna | 1999-01-19 |
| 5860160 | High speed FIFO mark and retransmit scheme using latches and precharge | Pidugu L. Narayana, Daniel Eric Cress, Ping Wu | 1999-01-12 |
| 5860118 | SRAM write partitioning | George M. Ansel, James E. Kelly | 1999-01-12 |
| 5852748 | Programmable read-write word line equality signal generation for FIFOs | Pidugu L. Narayana, Roland T. Knaack | 1998-12-22 |
| 5850568 | Circuit having plurality of carry/sum adders having read count, write count, and offset inputs to generate an output flag in response to FIFO fullness | Pidugu L. Narayana | 1998-12-15 |
| 5844423 | Half-full flag generator for synchronous FIFOs | Pidugu L. Narayana | 1998-12-01 |