Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12395175 | Level-shifter having a wide operating range, a fast output fall delay and improved rise time | Lalit Gupta, Jesse Wang | 2025-08-19 |
| 12131775 | Keeper-free volatile memory system | Lalit Gupta, Andreas Gotterba, Jesse Wang | 2024-10-29 |
| 11804262 | Area efficient memory cell read disturb mitigation | Lalit Gupta, Andreas Gotterba, Jesse Wang | 2023-10-31 |
| 6933757 | Timing method and apparatus for integrated circuit device | — | 2005-08-23 |
| 6751755 | Content addressable memory having redundancy capabilities | Eric H. Voelkel | 2004-06-15 |
| 6731566 | Single ended simplex dual port memory cell | Richard K. Chou, Andrew L. Hawkins | 2004-05-04 |
| 6697275 | Method and apparatus for content addressable memory test mode | Eric H. Voelkel | 2004-02-24 |
| 6661716 | Write method and circuit for content addressable memory | — | 2003-12-09 |
| 6647457 | Content addressable memory having prioritization of unoccupied entries | Eric H. Voelkel | 2003-11-11 |
| 6515884 | Content addressable memory having reduced current consumption | Eric H. Voelkel | 2003-02-04 |
| 6262912 | Single ended simplex dual port memory cell | Richard K. Chou, Andrew L. Hawkins | 2001-07-17 |
| 6240000 | Content addressable memory with reduced transient current | Eric H. Voelkel | 2001-05-29 |
| 6195277 | Multiple signal detection circuit | Eric H. Voelkel, Sow T. Chu | 2001-02-27 |
| 6181595 | Single ended dual port memory cell | Andrew L. Hawkins | 2001-01-30 |
| 6005795 | Single ended dual port memory cell | Andrew L. Hawkins | 1999-12-21 |
| 6005796 | Single ended simpler dual port memory cell | Richard K. Chou, Andrew L. Hawkins | 1999-12-21 |
| 6002283 | Apparatus for generating an asynchronous status flag with defined minimum pulse | — | 1999-12-14 |
| 5768196 | Shift-register based row select circuit with redundancy for a FIFO memory | Raymond E. Bloker, Andrew L. Hawkins | 1998-06-16 |
| 5765214 | Memory access method and apparatus and multi-plane memory device with prefetch | — | 1998-06-09 |
| 5715205 | Memory with a selectable data width and reduced decoding logic | — | 1998-02-03 |
| 5336938 | Apparatus for generating an asynchronous status flag with defined minimum pulse | — | 1994-08-09 |