Issued Patents All Time
Showing 26–34 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5828624 | Decoder circuit and method for disabling a number of columns or rows in a memory | William G. Baker, Jeffery Scott Hunt | 1998-10-27 |
| 5809339 | State machine design for generating half-full and half-empty flags in an asynchronous FIFO | Pidugu L. Narayana | 1998-09-15 |
| 5768196 | Shift-register based row select circuit with redundancy for a FIFO memory | Raymond E. Bloker, Stefan P. Sywyk | 1998-06-16 |
| 5751644 | Data transition detect write control | George M. Ansel, Jeffery Scott Hunt, Ping Wu, David Lindley | 1998-05-12 |
| 5712992 | State machine design for generating empty and full flags in an asynchronous FIFO | Pidugu L. Narayana | 1998-01-27 |
| 5673234 | Read bitline writer for fallthru in FIFO's | Muthukumar Nagarajan, Ajay Srikrishna | 1997-09-30 |
| 5661418 | Signal generation decoder circuit and method | Pidugu L. Narayana | 1997-08-26 |
| 5642318 | Testing method for FIFOS | Roland T. Knaack, Richard A Rodell, Jr. | 1997-06-24 |
| 5627797 | Full and empty flag generator for synchronous FIFOS | Pidugu L. Narayana | 1997-05-06 |