| 11657159 |
Identifying security vulnerabilities using modeled attribute propagation |
Matthew Michael Garcia Pardini, Bodo Hoppe, Zoltan T. Hidvegi |
2023-05-23 |
| 11443044 |
Targeted very long delay for increasing speculative execution progression |
Olaf K. Hendrickson, Matthew Michael Garcia Pardini |
2022-09-13 |
| 11205005 |
Identifying microarchitectural security vulnerabilities using simulation comparison with modified secret data |
Matthew Michael Garcia Pardini, Gregory W. Alexander, Jonathan T. Hsieh, Olaf K. Hendrickson |
2021-12-21 |
| 11106602 |
Memory blockade for verifying system security with respect to speculative execution |
Olaf K. Hendrickson, Matthew Michael Garcia Pardini |
2021-08-31 |
| 9734033 |
Implementing processor functional verification by generating and running constrained random irritator tests for multiple processor system and processor core with multiple threads |
Olaf K. Hendrickson, Yugi Morimoto, Michal Rimon |
2017-08-15 |
| 9720793 |
Implementing processor functional verification by generating and running constrained random irritator tests for multiple processor system and processor core with multiple threads |
Olaf K. Hendrickson, Yugi Morimoto, Michal Rimon |
2017-08-01 |
| 9389897 |
Exiting multiple threads of a simulation environment in a computer |
Fadi Y. Busaba, Mark S. Farrell, Lisa C. Heller |
2016-07-12 |
| 9218442 |
Firmware and hardware verification using Opcode comparison |
Christopher A. Krygowski, Timothy J. Slegel, Kai Weber |
2015-12-22 |
| 8484007 |
Method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model |
Wei-Yi Xiao, Vasantha R. Vuyyuru, Robert J. Adkins |
2013-07-09 |
| 8165864 |
Method, system and computer program product for verifying address generation, interlocks and bypasses |
Marvin J. Rich, James Lyle Schafer |
2012-04-24 |
| 7895538 |
System and method for providing a common instruction table |
David S. Hutton, James J. Bonanno, Chung-Lung K. Shum |
2011-02-22 |
