| 8165864 |
Method, system and computer program product for verifying address generation, interlocks and bypasses |
Michael P. Mullen, James Lyle Schafer |
2012-04-24 |
| 7856347 |
Facilitating simulation of a model within a distributed environment |
William K. Mellors |
2010-12-21 |
| 7444277 |
Facilitating simulation of a model within a distributed environment |
William K. Mellors |
2008-10-28 |
| 7412638 |
Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit |
Jay R. Herring |
2008-08-12 |
| 7409614 |
Method, system and program product for boundary I/O testing employing a logic built-in self-test of an integrated circuit |
Jay R. Herring |
2008-08-05 |
| 7409613 |
Simultaneous AC logic self-test of multiple clock domains |
Jay R. Herring, Ronald Linton |
2008-08-05 |
| 7272761 |
Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit |
Jay R. Herring |
2007-09-18 |
| 7272764 |
Method, system, and program product for boundary I/O testing employing a logic built-in self-test of an integrated circuit |
Jay R. Herring |
2007-09-18 |
| 7231334 |
Coupler interface for facilitating distributed simulation of a partitioned logic design |
William K. Mellors |
2007-06-12 |
| 7158925 |
Facilitating simulation of a model within a distributed environment |
William K. Mellors |
2007-01-02 |
| 7146587 |
Scalable logic self-test configuration for multiple chips |
Jay R. Herring |
2006-12-05 |
| 7137114 |
Dynamically transferring license administrative responsibilities from a license server to one or more other license servers |
William K. Mellors, Soon I. Joe, Ronald P. Checca |
2006-11-14 |
| 7124071 |
Partitioning a model into a plurality of independent partitions to be processed within a distributed environment |
William K. Mellors, Soon I. Joe |
2006-10-17 |
| 7085701 |
Size reduction techniques for vital compliant VHDL simulation models |
Ashutosh Misra |
2006-08-01 |
| 6817000 |
Delay correlation analysis and representation for vital complaint VHDL models |
Ashutosh Misra |
2004-11-09 |
