MC

Michael J. Colwell

Lsi Logic: 11 patents #141 of 1,957Top 8%
VL Virage Logic: 3 patents #19 of 67Top 30%
Overall (All Time): #355,949 of 4,157,543Top 9%
14
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7129562 Dual-height cell with variable width power rail architecture Tushar R. Gheewala, Henry H. Yang, Duane G. Breid 2006-10-31
6838713 Dual-height cell with variable width power rail architecture Tushar R. Gheewala, Henry H. Yang, Duane G. Breid 2005-01-04
6617621 Gate array architecture using elevated metal levels for customization Tushar R. Gheewala, Duane G. Breid, Deepak D. Sherlekar 2003-09-09
5917207 Programmable polysilicon gate array base cell architecture Teh-Kuin Lee, Jane C.T. Chiu, Abraham Yee, Stanley Yeh, Gobi R. Padmanabhan 1999-06-29
5843813 I/O driver design for simultaneous switching noise minimization and ESD performance enhancement Hua Wei, Randall Bach 1998-12-01
5777354 Low profile variable width input/output cells Gary Cheung, Elias Lozano, Trung Nguyen, Kevin Atkinson 1998-07-07
5773855 Microelectronic circuit including silicided field-effect transistor elements that bifunction as interconnects Gary Cheung, Paul Torgerson 1998-06-30
5760428 Variable width low profile gate array input/output architecture Stephen P. Roddy 1998-06-02
5728612 Method for forming minimum area structures for sub-micron CMOS ESD protection in integrated circuit structures without extra implant and mask steps, and articles formed thereby Hua Wei 1998-03-17
5698873 High density gate array base cell architecture Teh-Kuin Lee 1997-12-16
5691218 Method of fabricating a programmable polysilicon gate array base cell structure Teh-Kuin Lee, Jane C.T. Chiu, Abraham Yee, Stanley Yeh, Gobi R. Padmanabhan 1997-11-25
5670890 Switchable pull-ups and pull-downs for IDDQ testing of integrated circuits Rochit Rajsuman, Ray Abrishami, Zarir B. Sarkari 1997-09-23
5644251 Switchable pull-ups and pull-downs for IDDQ testing of integrated circuits Rochit Rajsuman, Ray Abrishami, Zarir B. Sarkari 1997-07-01
5552333 Method for designing low profile variable width input/output cells Gary Cheung, Elias Lozano, Trung Nguyen, Kevin Atkinson 1996-09-03