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Partial computer processor core shutoff |
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Congestion mitigation by wire ordering |
Diwesh Pandey, Sven Peyer |
2017-09-12 |
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Parsing data representative of a hardware design into commands of a hardware design environment |
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2014-06-17 |
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Method and system for calculating timing delay in a repeater network in an electronic circuit |
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2014-05-20 |
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Gate configuration determination and selection from standard cell library |
Thomas Buechner, Markus Olbrich, Philipp Panitz, Lei Wang |
2014-01-07 |
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Estimating power consumption of an electronic circuit |
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2013-12-17 |
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Signal repowering chip for 3-dimensional integrated circuit |
Sebastian Ehrenreich, Juergen Koehl |
2013-08-20 |
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2013-07-23 |
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Glitch power reduction |
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2013-03-26 |
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2013-02-19 |
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Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same |
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2012-07-31 |
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Structure for an integrated circuit design for reducing coupling between wires of an electronic circuit |
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2011-10-04 |
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Routing of wires of an electronic circuit |
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2011-09-06 |
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Test yield estimate for semiconductor products created from a library |
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2011-08-30 |
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Method and system for placement of electric circuit components in integrated circuit design |
Juergen Koehl |
2011-08-30 |
| 8006208 |
Reducing coupling between wires of an electronic circuit |
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2011-08-23 |
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Computer readable medium, system and associated method for designing integrated circuits with loop insertions |
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2011-08-09 |
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Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same |
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2011-07-19 |
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Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same |
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2011-06-14 |
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Via structure to improve routing of wires within an integrated circuit |
Ankit Gangwar, Juergen Koehl, Arun Kumar Mishra |
2011-06-14 |
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Method, system, and computer program product for coupled noise timing violation avoidance in detailed routing |
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2011-03-08 |
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Yield optimization in router for systematic defects |
Jeanne P. Bickford, Jason D. Hibbeler, Juergen Koehl, Daniel N. Maynard |
2008-07-08 |
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Test yield estimate for semiconductor products created from a library |
Jeanne P. Bickford, Jason D. Hibbeler, Juergen Koehl |
2008-06-10 |
| 7308669 |
Use of redundant routes to increase the yield and reliability of a VLSI layout |
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2007-12-11 |