Issued Patents All Time
Showing 25 most recent of 60 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12368137 | High bandwidth die to die interconnect with package area reduction | Chonghua Zhong, Jun Zhai | 2025-07-22 |
| 12322730 | Wafer reconstitution and die-stitching | Sanjay Dabral, Jun Zhai, Kwan-Yu Lai, Vidhya Ramachandran | 2025-06-03 |
| 12283549 | High density interconnection using fanout interposer chiplet | Jun Zhai, Chonghua Zhong | 2025-04-22 |
| 12261132 | Structure and method for sealing a silicon IC | Vidhya Ramachandran, Sanjay Dabral, SivaChandra Jangam, Jun Zhai | 2025-03-25 |
| 12249599 | Multiple chip module trenched lid and low coefficient of thermal expansion stiffener ring | Wei Chen, Jie Zhao, Jun Zhai, Po-Hao Chang, Hsien-Che Lin +1 more | 2025-03-11 |
| 12159835 | High density 3D interconnect configuration | Sanjay Dabral, Zhitao Cao, Jun Zhai | 2024-12-03 |
| 12119304 | Very fine pitch and wiring density organic side by side chiplet integration | Sanjay Dabral, Zhitao Cao | 2024-10-15 |
| 12087689 | Selectable monolithic or external scalable die-to-die interconnection system methodology | Sanjay Dabral, Jun Zhai, Jung-Cheng Yeh, Raymundo M. Camenforte, Thomas Hoffmann | 2024-09-10 |
| 11967528 | Structure and method for fabricating a computing system with an integrated voltage regulator module | Vidhya Ramachandran, Jun Zhai, Chonghua Zhong, Shawn Searles, Joseph T. DiBene, II +1 more | 2024-04-23 |
| 11862557 | Selectable monolithic or external scalable die-to-die interconnection system methodology | Sanjay Dabral, Jun Zhai, Jung-Cheng Yeh, Raymundo M. Camenforte, Thomas Hoffmann | 2024-01-02 |
| 11831312 | Systems and methods for implementing a scalable system | Sanjay Dabral, Bahattin Kilic, Jie Zhao, Suk-Kyu Ryu | 2023-11-28 |
| 11824015 | Structure and method for sealing a silicon IC | Vidhya Ramachandran, Sanjay Dabral, SivaChandra Jangam, Jun Zhai | 2023-11-21 |
| 11749631 | Electronic package including a hybrid thermal interface material and low temperature solder patterns to improve package warpage and reliability | Wei Chen, Jun Zhai | 2023-09-05 |
| 11735567 | Wafer reconstitution and die-stitching | Sanjay Dabral, Jun Zhai, Kwan-Yu Lai, Vidhya Ramachandran | 2023-08-22 |
| 11735526 | High density 3D interconnect configuration | Sanjay Dabral, Zhitao Cao, Jun Zhai | 2023-08-22 |
| 11728266 | Die stitching and harvesting of arrayed structures | Sanjay Dabral, Jun Zhai, Raymundo M. Camenforte | 2023-08-15 |
| 11670548 | Structure and method for fabricating a computing system with an integrated voltage regulator module | Vidhya Ramachandran, Jun Zhai, Chonghua Zhong, Shawn Searles, Joseph T. DiBene, II +1 more | 2023-06-06 |
| 11646302 | Multiple chip module trenched lid and low coefficient of thermal expansion stiffener ring | Wei Chen, Jie Zhao, Jun Zhai, Po-Hao Chang, Hsien-Che Lin +1 more | 2023-05-09 |
| 11594494 | High density interconnection using fanout interposer chiplet | Jun Zhai, Chonghua Zhong | 2023-02-28 |
| 11587909 | High bandwidth die to die interconnect with package area reduction | Chonghua Zhong, Jun Zhai | 2023-02-21 |
| 11404337 | Scalable extreme large size substrate integration | Chonghua Zhong, Jiongxin Lu, Jun Zhai | 2022-08-02 |
| 11309895 | Systems and methods for implementing a scalable system | Sanjay Dabral, Bahattin Kilic, Jie Zhao, Suk-Kyu Ryu | 2022-04-19 |
| 11309246 | High density 3D interconnect configuration | Sanjay Dabral, Zhitao Cao, Jun Zhai | 2022-04-19 |
| 11158621 | Double side mounted large MCM package with memory channel length reduction | Chonghua Zhong, Jun Zhai | 2021-10-26 |
| 11158607 | Wafer reconstitution and die-stitching | Sanjay Dabral, Jun Zhai, Kwan-Yu Lai, Vidhya Ramachandran | 2021-10-26 |