Issued Patents All Time
Showing 25 most recent of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12387089 | Efficient neural network accelerator dataflows | Yakun Shao, Rangharajan Venkatesan, Miaorong Wang, Daniel Smith, William J. Dally +2 more | 2025-08-12 |
| 11966835 | Deep neural network accelerator with fine-grained parallelism discovery | Ching-En Lee, Yakun Shao, Angshuman Parashar, Stephen W. Keckler | 2024-04-23 |
| 11847550 | Sparse convolutional neural network accelerator | William J. Dally, Angshuman Parashar, Stephen W. Keckler, Larry Robert Dennison | 2023-12-19 |
| 11769040 | Scalable multi-die deep learning system | Yakun Shao, Rangharajan Venkatesan, Nan Jiang, Brian Matthew Zimmer, Jason Lavar Clemons +5 more | 2023-09-26 |
| 11270197 | Efficient neural network accelerator dataflows | Yakun Shao, Rangharajan Venkatesan, Miaorong Wang, Daniel Smith, William J. Dally +2 more | 2022-03-08 |
| 10997496 | Sparse convolutional neural network accelerator | William J. Dally, Angshuman Parashar, Stephen W. Keckler, Larry Robert Dennison | 2021-05-04 |
| 10891538 | Sparse convolutional neural network accelerator | William J. Dally, Angshuman Parashar, Stephen W. Keckler, Larry Robert Dennison | 2021-01-12 |
| 10860922 | Sparse convolutional neural network accelerator | William J. Dally, Angshuman Parashar, Stephen W. Keckler, Larry Robert Dennison | 2020-12-08 |
| 10853276 | Executing distributed memory operations using processing elements connected by distributed channels | Bushra Ahsan, Michael C. Adler, Neal C. Crago, Aamer Jaleel, Angshuman Parashar +1 more | 2020-12-01 |
| 10528864 | Sparse convolutional neural network accelerator | William J. Dally, Angshuman Parashar, Stephen W. Keckler, Larry Robert Dennison | 2020-01-07 |
| 10331583 | Executing distributed memory operations using processing elements connected by distributed channels | Bushra Ahsan, Michael C. Adler, Neal C. Crago, Aamer Jaleel, Angshuman Parashar +1 more | 2019-06-25 |
| 10102124 | High bandwidth full-block write commands | Simon C. Steely, Jr., William C. Hasenplaugh, Samantika Subramaniam | 2018-10-16 |
| 9740617 | Hardware apparatuses and methods to control cache line coherence | Samantika S. Sury, Simon C. Steely, Jr., William C. Hasenplaugh, David A. Webb | 2017-08-22 |
| 9588889 | Domain state | Simon C. Steely, Jr., William C. Hasenplaugh | 2017-03-07 |
| 9418016 | Method and apparatus for optimizing the usage of cache memories | Simon C. Steely, Jr., William C. Hasenplaugh | 2016-08-16 |
| 9286128 | Processor scheduling with thread performance estimation on cores of different types | Aamer Jaleel, Kenzo Van Craeynest, Paolo Narvaez | 2016-03-15 |
| 9262327 | Signature based hit-predicting cache | Simon C. Steely, Jr., William C. Hasenplaugh, Aamer Jaleel, Carole-Jean Wu | 2016-02-16 |
| 9201792 | Short circuit of probes in a chain | Simon C. Steely, Jr., Samantika Subramaniam, William C. Hasenplaugh | 2015-12-01 |
| 9146871 | Retrieval of previously accessed data in a multi-core processor | Simon C. Steely, Jr., William C. Hasenplaugh | 2015-09-29 |
| 9037804 | Efficient support of sparse data structure access | Simon C. Steely, Jr., William C. Hasenplaugh | 2015-05-19 |
| 8769209 | Method and apparatus for achieving non-inclusive cache performance with inclusive caches | Aamer Jaleel, Simon C. Steely, Jr., Eric R. Borch, Malini K. Bhandaru | 2014-07-01 |
| 8769201 | Technique for controlling computing resources | William C. Hasenplaugh, Tryggve Fossum, Aamer Jaleel, Simon C. Steely, Jr. | 2014-07-01 |
| 8707012 | Implementing vector memory operations | Roger Espasa, Geoff Lowney, Roger Gramunt, Santiago Galan, Toni Juan +3 more | 2014-04-22 |
| 8316216 | Implementing vector memory operations | Roger Espasa, Geoff Lowney, Roger Gramunt, Santiago Galan, Toni Juan +3 more | 2012-11-20 |
| 7747932 | Reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system | Paul Racunas, Arijit Biswas, Shubhendu Sekhar Mukherjee, Steven Raasch | 2010-06-29 |