Issued Patents All Time
Showing 1–25 of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8860147 | Semiconductor interconnect | Amitava Chatterjee, Victor Sutcliffe | 2014-10-14 |
| 8581317 | SOI MuGFETs having single gate electrode level | Cloves Rinn Cleavelin, Andrew Marshall, Weize Xiong | 2013-11-12 |
| 8067792 | Memory device with memory cell including MuGFET and FIN capacitor | Weize Xiong, Andrew Marshall, Cloves Rinn Cleavelin | 2011-11-29 |
| 7968950 | Semiconductor device having improved gate electrode placement and decreased area design | — | 2011-06-28 |
| 7793186 | System and method for increasing the extent of built-in self-testing of memory and circuitry | Cloves Rinn Cleavelin, Andrew Marshall, Stephanie W. Butler | 2010-09-07 |
| 7768820 | Feedback structure for an SRAM cell | Theodore W. Houston | 2010-08-03 |
| 7759182 | Dummy active area implementation | Robert G. Fleck, Leif C. Olsen | 2010-07-20 |
| 7752518 | System and method for increasing the extent of built-in self-testing of memory and circuitry | Cloves Rinn Cleavelin, Andrew Marshall, Stephanie W. Butler | 2010-07-06 |
| 7683417 | Memory device with memory cell including MuGFET and fin capacitor | Weize Xiong, Andrew Marshall, Cloves Rinn Cleavelin | 2010-03-23 |
| 7539044 | Memory device with capacitor and diode | Andrew Marshall | 2009-05-26 |
| 7410840 | Building fully-depleted and bulk transistors on same chip | — | 2008-08-12 |
| 7410841 | Building fully-depleted and partially-depleted transistors on same chip | — | 2008-08-12 |
| 7198993 | Method of fabricating a combined fully-depleted silicon-on-insulator (FD-SOI) and partially-depleted silicon-on-insulator (PD-SOI) devices | Gabriel G. Barna, Olivier Faynot | 2007-04-03 |
| 6967110 | Sensitive test structure for assessing pattern anomalies | Richard L. Guldi, Anand J. Reddy | 2005-11-22 |
| 6919605 | Integrated circuit MOS transistor with reduced drain and source resistance | — | 2005-07-19 |
| 6687973 | Optimized metal fuse process | Melissa Hewson, Ricky Alan Jackson, Abha Singh, Toan Tran | 2004-02-10 |
| 6677240 | Method for patterning dense and isolated features on semiconductor devices | — | 2004-01-13 |
| 6180424 | Method for improving wafer sleuth capability by adding wafer rotation tracking | Richard L. Guldi | 2001-01-30 |
| 5821581 | Non-volatile memory cell structure and process for forming same | Cetin Kaya | 1998-10-13 |
| 5750427 | Non-volatile memory cell structure and process for forming same | Cetin Kaya | 1998-05-12 |
| 5595922 | Process for thickening selective gate oxide regions | Bert R. Riemenschneider, Richard A. Chapman, Andrew T. Appel | 1997-01-21 |
| 5557565 | Non-volatile memory cell structure and process for forming same | Cetin Kaya | 1996-09-17 |
| 5455184 | Method of making high speed EPROM containing graded source/drain profile | — | 1995-10-03 |
| 5451810 | Metal-to-metal antifuse structure | George R. Misium | 1995-09-19 |
| 5420060 | Method of making contract-free floating-gate memory array with silicided buried bitlines and with single-step defined floating gates | Manzur Gill | 1995-05-30 |