Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10707138 | High yield package assembly technique | Shiying Xiong, Thao H. T. Vo, Felino E. Pagaduan, Qi Xiang, Xiao-Yu Li | 2020-07-07 |
| 10032682 | Multi-die wafer-level test and assembly without comprehensive individual die singulation | Matthew H. Klein, Raghunandan Chaware | 2018-07-24 |
| 9865567 | Heterogeneous integration of integrated circuit device and companion device | Raghunandan Chaware, Ganesh Hariharan, Inderjit Singh, Amitava Majumdar | 2018-01-09 |
| 9761533 | Interposer-less stack die interconnect | Raghunandan Chaware, Amitava Majumdar, Inderjit Singh | 2017-09-12 |
| 9385106 | Method for providing charge protection to one or more dies during formation of a stacked silicon device | Raghunandan Chaware, Inderjit Singh, Ganesh Hariharan | 2016-07-05 |
| 9372956 | Increased usable programmable device dice | Yuezhen Fan, Eric J. Thorne, Xiao-Yu Li, Stephen M. Trimberger | 2016-06-21 |
| 9341668 | Integrated circuit package testing | Ganesh Hariharan, Raghunandan Chaware, Inderjit Singh, Eric J. Thorne, David E. Schweigler | 2016-05-17 |
| 9214433 | Charge damage protection on an interposer for a stacked die assembly | Qi Xiang, Xiao-Yu Li, Cinti X. Chen | 2015-12-15 |
| 8900987 | Method for removing bumps from incomplete and defective interposer dies for stacked silicon interconnect technology (SSIT) devices | Inderjit Singh, Raghunandan Chaware, Ganesh Hariharan | 2014-12-02 |
| 8212576 | Method and apparatus for self-regulated burn-in of an integrated circuit | Jae-Weon Cho, Michael M. Matera, Jongheon Jeong | 2012-07-03 |
| 7039842 | Measuring propagation delays of programmable logic devices | Trent Whitten, Mose Wahlstrom | 2006-05-02 |
| 5517153 | Power supply isolation and switching circuit | Rong Yin | 1996-05-14 |