Issued Patents All Time
Showing 25 most recent of 70 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12307224 | Cross-layer power optimization of program code and/or software architecture | Dinesh Kumar, Colleen Ann Weller, Margaret Annabelle Allen, Addison Daniel Ferrari | 2025-05-20 |
| 11687254 | Host synchronized autonomous data chip address sequencer for a distributed buffer memory system | Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Jie Zheng | 2023-06-27 |
| 11587600 | Address/command chip controlled data chip address sequencing for a distributed memory buffer system | Steven R. Carlough, Susan M. Eickhoff, Warren E. Maule, Patrick J. Meaney, Stephen J. Powell +1 more | 2023-02-21 |
| 11442829 | Packeted protocol device test system | Ryan Patrick King, Kevin M. Mcilvain | 2022-09-13 |
| 11379123 | Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system | Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Jie Zheng | 2022-07-05 |
| 11099601 | Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface | Steven R. Carlough, Susan M. Eickhoff, Michael B. Spear, Stephen D. Wyatt | 2021-08-24 |
| 11088782 | Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection | Steven R. Carlough, Patrick J. Meaney | 2021-08-10 |
| 10976939 | Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system | Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Jie Zheng | 2021-04-13 |
| 10771068 | Reducing chip latency at a clock boundary by reference clock phase adjustment | Steven R. Carlough, Susan M. Eickhoff, Michael W. Harper, Michael B. Spear | 2020-09-08 |
| 10747442 | Host controlled data chip address sequencing for a distributed memory buffer system | Steven R. Carlough, Susan M. Eickhoff, Warren E. Maule, Patrick J. Meaney, Stephen J. Powell +1 more | 2020-08-18 |
| 10698440 | Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface | Steven R. Carlough, Susan M. Eickhoff, Michael B. Spear, Stephen D. Wyatt | 2020-06-30 |
| 10649511 | Scalable data collection for system management | Irving G. Baysah, John S. Dodson, Karthick Rajamani, Eric E. Retter, Scot H. Rider +3 more | 2020-05-12 |
| 10642535 | Register access in a distributed memory buffer system | Steven R. Carlough, Markus Cebulla, Susan M. Eickhoff, Logan I. Friedman, Patrick J. Meaney +2 more | 2020-05-05 |
| 10541782 | Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection | Steven R. Carlough, Patrick J. Meaney | 2020-01-21 |
| 10534555 | Host synchronized autonomous data chip address sequencer for a distributed buffer memory system | Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Jie Zheng | 2020-01-14 |
| 10530523 | Dynamically adjustable cyclic redundancy code rates | Steven R. Carlough, Patrick J. Meaney | 2020-01-07 |
| 10530396 | Dynamically adjustable cyclic redundancy code types | Steven R. Carlough, Patrick J. Meaney | 2020-01-07 |
| 10489069 | Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system | Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Jie Zheng | 2019-11-26 |
| 10419035 | Use of multiple cyclic redundancy codes for optimized fail isolation | Steven R. Carlough, Patrick J. Meaney | 2019-09-17 |
| 10395698 | Address/command chip controlled data chip address sequencing for a distributed memory buffer system | Steven R. Carlough, Susan M. Eickhoff, Warren E. Maule, Patrick J. Meaney, Stephen J. Powell +1 more | 2019-08-27 |
| 10393805 | JTAG support over a broadcast bus in a distributed memory buffer system | Logan I. Friedman, Nicholas Rolfe, Susan M. Eickhoff, Steven R. Carlough, Markus Cebulla +1 more | 2019-08-27 |
| 10353606 | Partial data replay in a distributed memory buffer system | Susan M. Eickhoff, Steven R. Carlough, Patrick J. Meaney, Stephen J. Powell, Jie Zheng | 2019-07-16 |
| 10317964 | Scalable data collection for system management | Irving G. Baysah, John S. Dodson, Karthick Rajamani, Eric E. Retter, Scot H. Rider +3 more | 2019-06-11 |
| 10162773 | Double data rate (DDR) memory read latency reduction | Steven R. Carlough, Susan M. Eickhoff, Michael B. Spear, Stephen D. Wyatt | 2018-12-25 |
| 10134455 | Efficient calibration of a data eye for memory devices | John S. Bialas, Jr., David D. Cadigan, Stephen P. Glancy, Warren E. Maule | 2018-11-20 |