Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11907124 | Using a shadow copy of a cache in a cache hierarchy | Yair Fried, Aaron Tsai, Christian Jacobi, Timothy C. Bronson, Chung-Lung K. Shum | 2024-02-20 |
| 11157281 | Prefetching data based on register-activity patterns | Yossi Shapira, Yair Fried, Amir Turi | 2021-10-26 |
| 11144321 | Store hit multiple load side register for preventing a subsequent store memory violation | Yair Fried, Jonathan T. Hsieh, James J. Bonanno, Gregory W. Alexander | 2021-10-12 |
| 11029950 | Reducing latency of common source data movement instructions | Yossi Shapira, Yair Fried, Amir Turi | 2021-06-08 |
| 10977040 | Heuristic invalidation of non-useful entries in an array | James R. Cuffney, Adam B. Collura, James J. Bonanno, Jang-Soo Lee, Yair Fried +1 more | 2021-04-13 |
| 10970214 | Selective downstream cache processing for data access | Willm Hinrichs, Markus Kaltenbach, Martin Recktenwald | 2021-04-06 |
| 10956328 | Selective downstream cache processing for data access | Willm Hinrichs, Markus Kaltenbach, Martin Recktenwald | 2021-03-23 |
| 10929142 | Making precise operand-store-compare predictions to avoid false dependencies | Gregory W. Alexander, James J. Bonanno, Adam B. Collura, James R. Cuffney, Yair Fried +4 more | 2021-02-23 |
| 10691604 | Minimizing cache latencies using set predictors | Dwifuzi Coe, Christian Jacobi, Markus Kaltenbach, Martin Recktenwald | 2020-06-23 |
| 10684951 | Minimizing cache latencies using set predictors | Dwifuzi Coe, Christian Jacobi, Markus Kaltenbach, Martin Recktenwald | 2020-06-16 |
| 10678549 | Executing processor instructions using minimal dependency queue | Avraham Ayzenfeld, Amir Turi | 2020-06-09 |
| 10649777 | Hardware-based data prefetching based on loop-unrolled instructions | Yossi Shapira, Gregory Miaskovsky, Yair Fried | 2020-05-12 |
| 10572624 | Modified design debugging using differential trace back | Erez Barak, Shlomit Koyfman, Ziv Nevo, Osher Yifrach | 2020-02-25 |
| 10417127 | Selective downstream cache processing for data access | Willm Hinrichs, Markus Kaltenbach, Martin Recktenwald | 2019-09-17 |
| 10409724 | Selective downstream cache processing for data access | Willm Hinrichs, Markus Kaltenbach, Martin Recktenwald | 2019-09-10 |
| 10360030 | Efficient pointer load and format | Martin Recktenwald, Christian Zoellin, Aaron Tsai | 2019-07-23 |
| 10353707 | Efficient pointer load and format | Martin Recktenwald, Christian Zoellin, Aaron Tsai | 2019-07-16 |
| 10324815 | Error checking of a multi-threaded computer processor design under test | Erez Barak, Oz Dov Hershkovitz, Gilad Merran | 2019-06-18 |
| 10169041 | Efficient pointer load and format | Martin Recktenwald, Christian Zoellin, Aaron Tsai | 2019-01-01 |