ES

Edward W. Sengle

IBM: 9 patents #11,918 of 70,183Top 20%
Overall (All Time): #585,589 of 4,157,543Top 15%
9
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7132325 Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure Wagdi W. Abadeer, Eric Adler, Jeffrey S. Brown, Robert J. Gauthier, Jr., Jonathan M. McKenna +2 more 2006-11-07
6770907 Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure Wagdi W. Abadeer, Eric Adler, Jeffrey S. Brown, Robert J. Gauthier, Jr., Jonathan M. McKenna +2 more 2004-08-03
6624031 Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure Wagdi W. Abadeer, Eric Adler, Jeffrey S. Brown, Robert J. Gauthier, Jr., Jonathan M. McKenna +2 more 2003-09-23
6394638 Trench isolation for active areas and first level conductors Mark D. Jaffe, Daniel N. Maynard, Mark A. Lavin, Eric J. White, John A. Bracchitta 2002-05-28
6147394 Method of photolithographically defining three regions with one mask step and self aligned isolation structure formed thereby James A. Bruce, Steven J. Holmes, Robert K. Leidy, Walter E. Mlynko 2000-11-14
6140171 FET device containing a conducting sidewall spacer for local interconnect and method for its fabrication Archibald J. Allen, Jerome B. Lasky, Randy W. Mann, John J. Pekarik, Jed H. Rankin +1 more 2000-10-31
6063687 Formation of trench isolation for active areas and first level conductors Mark D. Jaffe, Daniel N. Maynard, Mark A. Lavin, Eric J. White, John A. Bracchitta 2000-05-16
5972570 Method of photolithographically defining three regions with one mask step and self aligned isolation structure formed thereby James A. Bruce, Steven J. Holmes, Robert K. Leidy, Walter E. Mlynko 1999-10-26
5734192 Trench isolation for active areas and first level conductors Mark D. Jaffe, Daniel N. Maynard, Mark A. Lavin, Eric J. White, John A. Bracchitta 1998-03-31