| 8589629 |
Method for way allocation and way locking in a cache |
Jonathan Owen, Guhan Krishnan, Carl Dietz, William Kurt Lewchuk, Alexander J. Branover |
2013-11-19 |
| 7502969 |
Method and apparatus for analyzing digital circuits |
Holger Eisenreich, Kai Eichhorn |
2009-03-10 |
| 6351797 |
Translation look-aside buffer for storing region configuration bits and method of operation |
Darren Bensley, Daniel W. Green |
2002-02-26 |
| 5963984 |
Address translation unit employing programmable page size |
Raul A. Garibay, Jr., Marc A. Quattromani, Mark Bluhm |
1999-10-05 |
| 5752274 |
Address translation unit employing a victim TLB |
Raul A. Garibay, Jr., Marc A. Quattromani |
1998-05-12 |
| 5745721 |
Partitioned addressing apparatus for vector/scalar registers |
Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more |
1998-04-28 |
| 5717881 |
Data processing system for processing one and two parcel instructions |
Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more |
1998-02-10 |
| 5706490 |
Method of processing conditional branch instructions in scalar/vector processor |
Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more |
1998-01-06 |
| 5659706 |
Vector/scalar processor with simultaneous processing and instruction cache filling |
Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more |
1997-08-19 |
| 5640524 |
Method and apparatus for chaining vector instructions |
Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more |
1997-06-17 |
| 5623650 |
Method of processing a sequence of conditional vector IF statements |
Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more |
1997-04-22 |
| 5598547 |
Vector processor having functional unit paths of differing pipeline lengths |
Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more |
1997-01-28 |
| 5561784 |
Interleaved memory access system having variable-sized segments logical address spaces and means for dividing/mapping physical address into higher and lower order addresses |
Steve S. Chen, Frederick J. Simmons, George A. Spix, Jimmie R. Wilson, Edward C. Miller +1 more |
1996-10-01 |
| 5544337 |
Vector processor having registers for control by vector resisters |
Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more |
1996-08-06 |
| 5524255 |
Method and apparatus for accessing global registers in a multiprocessor system |
George A. Spix, Edward C. Miller, Robert E. Strout, II, Anthony R. Schooler, Alexander A. Silbey +4 more |
1996-06-04 |
| 5430884 |
Scalar/vector processor |
Andrew Everett Phelps, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more |
1995-07-04 |
| 5428803 |
Method and apparatus for a unified parallel processing architecture |
Steve S. Chen, George A. Spix, Edward C. Priest, John Wastlick, James M. VanDyke |
1995-06-27 |
| 5253359 |
Control and maintenance subsystem network for use with a multiprocessor computer system |
George A. Spix, Glen L. Collier, G. Joseph Throop, David L. Clounch, Cris J. Rhea |
1993-10-12 |
| 5239629 |
Dedicated centralized signaling mechanism for selectively signaling devices in a multiprocessor system |
Edward C. Miller, George A. Spix, Anthony R. Schooler, Alexander A. Silbey, Andrew Everett Phelps |
1993-08-24 |
| 5208914 |
Method and apparatus for non-sequential resource access |
Jimmie R. Wilson, Steve S. Chen, Roger E. Eckert, Richard E. Hessel, Andrew Everett Phelps +2 more |
1993-05-04 |
| 5197130 |
Cluster architecture for a highly parallel scalar/vector multiprocessor system |
Steve S. Chen, Frederick J. Simmons, George A. Spix, Jimmie R. Wilson, Edward C. Miller +1 more |
1993-03-23 |
| 5175862 |
Method and apparatus for a special purpose arithmetic boolean unit |
Andrew Everett Phelps, Michael A. Woodsmansee |
1992-12-29 |
| 5165038 |
Global registers for a multiprocessor system |
George A. Spix, Edward C. Miller, Robert E. Strout, II, Anthony R. Schooler, Alexander A. Silbey +4 more |
1992-11-17 |
| 5055707 |
Method and apparatus for single step clocking on signal paths longer than a clock cycle |
— |
1991-10-08 |
| 4953079 |
Cache memory address modifier for dynamic alteration of cache block fetch sequence |
William P. Ward |
1990-08-28 |