| 11853668 |
FPGA implementation interleaved with FPGA overlay architectures for emulation |
Ngai Ngai William Hung |
2023-12-26 |
| 11687831 |
Method, product, and apparatus for a multidimensional processing array for hardware acceleration of convolutional neural network inference |
Ngai Ngai William Hung, Michael Patrick Zimmer, Yong Liu |
2023-06-27 |
| 11676068 |
Method, product, and apparatus for a machine learning process leveraging input sparsity on a pixel by pixel basis |
Michael Patrick Zimmer, Ngai Ngai William Hung, Yong Liu |
2023-06-13 |
| 11615320 |
Method, product, and apparatus for variable precision weight management for neural networks |
Ngai Ngai William Hung, Michael Patrick Zimmer, Yong Liu |
2023-03-28 |
| 11468218 |
Information theoretic subgraph caching |
Ngai Ngai William Hung |
2022-10-11 |
| 10762262 |
Multi-dimensional constraint solver using modified relaxation process |
In-Ho Moon, Qiang Qiang |
2020-09-01 |
| 10372856 |
Optimizing constraint solving by rewriting at least one bit-slice constraint |
Ngai Ngai William Hung, Qiang Qiang, Guillermo Maturana, Jasvinder Singh |
2019-08-06 |
| 10325046 |
Formal method for clock tree analysis and optimization |
Lingyi Liu, Ngai Ngai William Hung, Sitanshu Seth, Leonid Alexander Broukhis |
2019-06-18 |
| 9958917 |
Generalized resettable memory |
Ngai Ngai William Hung |
2018-05-01 |
| 9720792 |
Information theoretic caching for dynamic problem generation in constraint solving |
Ngai Ngai William Hung |
2017-08-01 |
| 9202005 |
Development and debug environment in a constrained random verification |
Aijun Hu, Na Xing, Jason Chen, Ngai Ngai William Hung |
2015-12-01 |
| 9195634 |
Optimizing constraint solving by rewriting at least one modulo constraint |
Ngai Ngai William Hung, Qiang Qiang, Guillermo Maturana, Jasvinder Singh |
2015-11-24 |
| 9098665 |
Prioritized soft constraint solving |
Ganapathy Parthasarathy |
2015-08-04 |
| 9069699 |
Identifying inconsistent constraints |
Soe Myint, Ngai Ngai William Hung, Rajarshi Mukherjee |
2015-06-30 |
| 8904320 |
Solving multiplication constraints by factorization |
Vijay Anand R. Korthikanti |
2014-12-02 |
| 8479128 |
Technique for honoring multi-cycle path semantics in RTL simulation |
Kaushik De, Badri P. Gopalan |
2013-07-02 |
| 8413089 |
Performing implication and decision making using multiple value systems during constraint solving |
Qiang Qiang |
2013-04-02 |
| 8370273 |
Method and apparatus for constructing a canonical representation |
Ngai Ngai William Hung, Jasvinder Singh |
2013-02-05 |
| 8099690 |
Adaptive state-to-symbolic transformation in a canonical representation |
Ngai Ngai William Hung, Jasvinder Singh, Qiang Qiang |
2012-01-17 |
| 7984354 |
Generating responses to patterns stimulating an electronic circuit with timing exception paths |
Kun-Han Tsai, Mark Kassab, Janusz Rajski |
2011-07-19 |
| 7555689 |
Generating responses to patterns stimulating an electronic circuit with timing exception paths |
Kun-Han Tsai, Mark Kassab, Janusz Rajski |
2009-06-30 |
| 7036063 |
Generalized fault model for defects and circuit marginalities |
Sandip Kundu, Sanjay Sengupta |
2006-04-25 |
| 6311317 |
Pre-synthesis test point insertion |
Ajay Khoche, Harbinder Singh, Denis Martin |
2001-10-30 |