Issued Patents All Time
Showing 25 most recent of 106 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12165688 | Flash memory devices including dram | Yankang He, Walter Di Francesco, Luca Nubile | 2024-12-10 |
| 12136607 | Semiconductor devices including stacked dies with interleaved wire bonds and associated systems and methods | Koichi Kawai, Raj K. Bansal, Takehiro Hasegawa | 2024-11-05 |
| 12079479 | Memory device with multiple input/output interfaces | Jonathan S. Parry | 2024-09-03 |
| 12080644 | Microelectronic devices including staircase structures, and related memory devices and electronic systems | Qui Vi Nguyen | 2024-09-03 |
| 12007860 | Salvaging bad blocks in a memory device | Sri Rama Namala, Lu Tong, Kristopher Kopel, Sheng-Huang Lee | 2024-06-11 |
| 11875861 | Memory cell sensing | Hao Thai Nguyen | 2024-01-16 |
| 11861236 | Asymmetric plane driver circuits in a multi-plane memory device | Kalyan C. Kavalipurapu, Shigekazu Yamada | 2024-01-02 |
| 11791003 | Distributed compaction of logical states to reduce program time | Kalyan C. Kavalipurapu, George Matamis, Yingda Dong | 2023-10-17 |
| 11670346 | Memory cell programming including applying programming pulses of different pulse widths to different access lines | Michele Piccardi, Qui Vi Nguyen | 2023-06-06 |
| 11537484 | Salvaging bad blocks in a memory device | Sri Rama Namala, Lu Tong, Kristopher Kopel, Sheng-Huang Lee | 2022-12-27 |
| 11508444 | Memory cell sensing | Hao Thai Nguyen | 2022-11-22 |
| 11488677 | Distributed compaction of logical states to reduce program time | Kalyan C. Kavalipurapu, George Matamis, Yingda Dong | 2022-11-01 |
| 11437318 | Microelectronic devices including staircase structures, and related memory devices and electronic systems | Qui Vi Nguyen | 2022-09-06 |
| 11398256 | Local bit lines and methods of selecting the same to access memory elements in cross-point arrays | Christophe J. Chevallier, Darrell Rinerson, Seow Fong Lim, Sri Rama Namala | 2022-07-26 |
| 11354067 | Asymmetric plane driver circuits in a multi-plane memory device | Kalyan C. Kavalipurapu, Shigekazu Yamada | 2022-06-07 |
| 11144218 | Array voltage regulating technique to enable data operations on large memory arrays with resistive memory elements | — | 2021-10-12 |
| 11087841 | Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations | Bruce L. Bateman | 2021-08-10 |
| 11069386 | Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory | Christophe J. Chevallier, Seow Fong Lim | 2021-07-20 |
| 11011226 | Access signal adjustment circuits and methods for memory cells in a cross-point array | Christophe J. Chevallier | 2021-05-18 |
| 10971224 | High voltage switching circuitry for a cross-point array | Christophe J. Chevallier | 2021-04-06 |
| 10908210 | Die crack detection | Kirubakaran Periyannan, Naresh Battula | 2021-02-02 |
| 10788993 | Array voltage regulating technique to enable data operations on large memory arrays with resistive memory elements | — | 2020-09-29 |
| 10672467 | High voltage switching circuitry for a cross-point array | Christophe J. Chevallier | 2020-06-02 |
| 10650870 | Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory | Christophe J. Chevallier, Seow Fong Lim | 2020-05-12 |
| 10622028 | Local bit lines and methods of selecting the same to access memory elements in cross-point arrays | Christophe J. Chevallier, Darrell Rinerson, Seow Fong Lim, Sri Rama Namala | 2020-04-14 |