Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12099943 | Method of matching employers with job seekers including emotion recognition | — | 2024-09-24 |
| 12007403 | Automated diagnostic analyzers having rear accessible track systems and related methods | Brian L. Ochranek, David C. Arnquist, Takehiko Oonuma, Hirotoshi Tahara, Naoto Sato | 2024-06-11 |
| 11328232 | Method of matching employers with job seekers | Sanford G. Kulkin | 2022-05-10 |
| 11328231 | Method of matching employers with job seekers | Sanford G. Kulkin | 2022-05-10 |
| 11125766 | Automated diagnostic analyzers having rear accessible track systems and related methods | Brian L. Ochranek, David C. Arnquist, Takehiko Oonuma, Hirotoshi Tahara, Naoto Sato | 2021-09-21 |
| 11004019 | Method of matching employers with job seekers | Sanford G. Kulkin | 2021-05-11 |
| 10743561 | Apparatus and method for making a frozen confectionary product | — | 2020-08-18 |
| 10267818 | Automated diagnostic analyzers having rear accessible track systems and related methods | Brian L. Ochranek, David C. Arnquist, Takehiko Oonuma, Hirotoshi Tahara, Naoto Sato | 2019-04-23 |
| 10062713 | Devices and methods for fully depleted silicon-on-insulator back biasing | — | 2018-08-28 |
| 9335338 | Automated diagnostic analyzers having rear accessible track systems and related methods | Brian L. Ochranek, David C. Arnquist, Takehiko Oonuma, Hirotoshi Tahara, Naoto Sato | 2016-05-10 |
| 9064785 | Electronic device including a capacitor and a process of forming the same | Edward O. Travis | 2015-06-23 |
| 9000507 | Method and system for recovering from transistor aging using heating | Mehul D. Shroff | 2015-04-07 |
| 8426263 | Patterning a gate stack of a non-volatile memory (NVM) with formation of a metal-oxide-semiconductor field effect transistor (MOSFET) | James W. Miller | 2013-04-23 |
| 8420480 | Patterning a gate stack of a non-volatile memory (NVM) with formation of a gate edge diode | — | 2013-04-16 |
| 8415217 | Patterning a gate stack of a non-volatile memory (NVM) with formation of a capacitor | Mehul D. Shroff | 2013-04-09 |
| 7985655 | Through-via and method of forming | — | 2011-07-26 |
| 7923369 | Through-via and method of forming | — | 2011-04-12 |
| 7589550 | Semiconductor device test system having reduced current leakage | — | 2009-09-15 |
| 7353953 | Packaging of multiple fluid receptacles | Davis Freeman, Robert Novick | 2008-04-08 |
| 7238579 | Semiconductor device for reducing photovolatic current | Edward O. Travis | 2007-07-03 |
| 6956281 | Semiconductor device for reducing photovolatic current | Edward O. Travis | 2005-10-18 |
| 6838354 | Method for forming a passivation layer for air gap formation | Cindy Goldberg, Stanley M. Filipiak, John C. Flake, Yeong-Jyh T. Lii, Yuri Solomentsev +3 more | 2005-01-04 |
| 6764919 | Method for providing a dummy feature and structure thereof | Kathleen C. Yu, Edward O. Travis | 2004-07-20 |
| 6551919 | Method for forming a dual inlaid copper interconnect structure | Suresh Venkatesan, Mohammed Rabiul Islam | 2003-04-22 |
| 6489083 | Selective sizing of features to compensate for resist thickness variations in semiconductor devices | Edward O. Travis, Sejal Chheda, Ruiqi Tian | 2002-12-03 |