Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12204908 | Storing incidental branch predictions to reduce latency of misprediction recovery | Marius Evers, Douglas R. Williams, Sudherssen Kalaiselvan | 2025-01-21 |
| 12204911 | Retire queue compression | Matthew T. Sobel, Joshua James Lindner, Neil N. Marketkar, Kai Troester, Emil Talpes | 2025-01-21 |
| 11620224 | Instruction cache prefetch throttle | Aparna Thyagarajan, Marius Evers, Angelo Wong, William E. Jones | 2023-04-04 |
| 11599359 | Methods and systems for utilizing a master-shadow physical register file based on verified activation | Arun A. Nair, Emil Talpes, Srikanth Arekapudi, Rajesh Kumar Arunachalam | 2023-03-07 |
| 11579884 | Instruction address translation and caching for primary and alternate branch prediction paths | Steven R. Havlir, Robert B. Cohen | 2023-02-14 |
| 11416256 | Selectively performing ahead branch prediction based on types of branch instructions | Marius Evers, Aparna Thyagarajan | 2022-08-16 |
| 11144324 | Retire queue compression | Matthew T. Sobel, Joshua James Lindner, Neil N. Marketkar, Kai Troester, Emil Talpes | 2021-10-12 |
| 10896044 | Low latency synchronization for operation cache and instruction cache fetching and decoding instructions | Marius Evers, Dhanaraj Bapurao Tavare, Arunachalam Annamalai, Donald A. Priore, Douglas R. Williams | 2021-01-19 |
| 10732979 | Selectively performing ahead branch prediction based on types of branch instructions | Marius Evers, Aparna Thyagarajan | 2020-08-04 |
| 10635591 | Systems and methods for selectively filtering, buffering, and processing cache coherency probes | Anthony Jarvis | 2020-04-28 |
| 8347250 | Method and apparatus for addressing and improving holds in logic networks | George A. Gonzalez, Pete J. Hannan, William McGee, Vasant K. Palisetti | 2013-01-01 |