Issued Patents All Time
Showing 26–50 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7009894 | Dynamically activated memory controller data termination | Anoop Mukker, Dave Freker, Navneet Dour | 2006-03-07 |
| 6983339 | Method and apparatus for processing interrupts of a bus | Jeffrey L. Rabe, Satish B. Acharya, Serafin E. Garcia, David J. Harriman | 2006-01-03 |
| 6961823 | Stream-down prefetching cache | Herbert Hum | 2005-11-01 |
| 6915407 | Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller | Srinivasan T. Rajappa, Romesh Trivedi, Rajagopal Subramanian, Serafin E. Garcia | 2005-07-05 |
| 6910114 | Adaptive idle timer for a memory device | Suryaprasad Kareenahalli, Mihir Shah | 2005-06-21 |
| 6784890 | Accelerated graphics port expedite cycle throttling control mechanism | Brian Bergeson, Vincent E. VonBokern | 2004-08-31 |
| 6782435 | Device for spatially and temporally reordering for data between a processor, memory and peripherals | Serafin E. Garcia, Steve John Clohset, Mikal C. Hunsaker | 2004-08-24 |
| 6748513 | Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller | Srinivasan T. Rajappa, Romesh Trivedi, Rajagopal Subramanian, Serafin E. Garcia | 2004-06-08 |
| 6694390 | Managing bus transaction dependencies | Serafin E. Garcia | 2004-02-17 |
| 6658533 | Method and apparatus for write cache flush and fill mechanisms | Steven J. Clohset | 2003-12-02 |
| 6643743 | Stream-down prefetching cache | Herbert Hum | 2003-11-04 |
| 6584526 | Inserting bus inversion scheme in bus path without increased access latency | Serafin E. Garcia, Steven J. Clohset | 2003-06-24 |
| 6523093 | Prefetch buffer allocation and filtering system | Steven J. Clohset | 2003-02-18 |
| 6502150 | Method and apparatus for resource sharing in a multi-processor system | Narendra S. Khandekar, Steve John Clohset | 2002-12-31 |
| 6499085 | Method and system for servicing cache line in response to partial cache line request | David J. Harriman, Zdzislaw A. Wirkus, Satish B. Acharya | 2002-12-24 |
| 6470238 | Method and apparatus to control device temperature | Puthiya K. Nizar, David J. McDonnell, Brian K. Langendorf, Michael G. LaTondre, Jeff Rabe +2 more | 2002-10-22 |
| 6385703 | Speculative request pointer advance for fast back-to-back reads | Narendra S. Khandekar, David D. Lent | 2002-05-07 |
| 6314472 | Abort of DRAM read ahead when PCI read multiple has ended | Tuong Trieu, David D. Lent, Ashish S. Gadagkar, Vincent E. VonBokern | 2001-11-06 |
| 6314497 | Apparatus and method for maintaining cache coherency in a memory system | Steve John Clohset, Narendra S. Khandekar | 2001-11-06 |
| 6243781 | Avoiding deadlock by storing non-posted transactions in an auxiliary buffer when performing posted and non-posted bus transactions from an outbound pipe | Wishwesh Anil Gandhi, Tuong Trieu, Ashish S. Gadagkar, David D. Lent | 2001-06-05 |
| 6237055 | Avoiding livelock when performing a long stream of transactions | Tuong Trieu, David D. Lent, Ashish S. Gadagkar | 2001-05-22 |
| 6215703 | In order queue inactivity timer to improve DRAM arbiter operation | Vincent Edward Von Bokern | 2001-04-10 |
| 6202112 | Arbitration methods to avoid deadlock and livelock when performing transactions across a bridge | Ashish S. Gadagkar, Narendra S. Khandekar, David D. Lent | 2001-03-13 |
| 6192455 | Apparatus and method for preventing access to SMRAM space through AGP addressing | Vincent E. VonBokern | 2001-02-20 |
| 6181619 | Selective automatic precharge of dynamic random access memory banks | Vincent E. VonBokern, David E. Freker | 2001-01-30 |