Issued Patents All Time
Showing 51–74 of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10559348 | System, apparatus and method for simultaneous read and precharge of a memory | Lavanya Subramanian, Kaushik Vaidyanathan, Anant Vithal Nori, Tanay Karnik | 2020-02-11 |
| 10496413 | Efficient hardware-based extraction of program instructions for critical paths | Jayesh Gaur, Pooja Roy, Hong Wang, Ronak Singhal | 2019-12-03 |
| 10430198 | Dynamic detection and prediction for store-dependent branches | Saurabh Gupta, Rahul Pal, Niranjan Soundararajan, Ragavendra Natarajan | 2019-10-01 |
| 10423422 | Branch predictor with empirical branch bias override | Niranjan Soundararajan, Rahul Pal, Ragavendra Natarajan | 2019-09-24 |
| 10402413 | Hardware accelerator for selecting data elements | Mahesh Mamidipaka, Srivatsava Jandhyala, Anish N K, Nagadastagiri Reddy C | 2019-09-03 |
| 10331582 | Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein the threshold is derived from latency of write to LLC and main memory retrieval time | Ishwar Bhati, Huichu Liu, Jayesh Gaur, Kunal Kishore Korgaonkar, Sasikanth Manipatruni +3 more | 2019-06-25 |
| 10318834 | Optimized image feature extraction | Gurpreet Singh Kalsi, Om Ji Omer, Biji George, Gopi Neela, Dipan Kumar Mandal | 2019-06-11 |
| 10268600 | System, apparatus and method for prefetch-aware replacement in a cache memory hierarchy of a processor | Jayesh Gaur, Sanjay Ganapathy | 2019-04-23 |
| 10191689 | Systems and methods for page management using local page information | Sriseshan Srikanth, Lavanya Subramanian | 2019-01-29 |
| 10176124 | Scoreboard approach to managing idle page close timeout duration in memory | Sriseshan Srikanth, Lavanya Subramanian | 2019-01-08 |
| 10162756 | Memory-efficient last level cache architecture | Jayesh Gaur, Ayan Mandal, Anant Vithal Nori | 2018-12-25 |
| 10013352 | Partner-aware virtual microsectoring for sectored cache architectures | Jayesh Gaur, Mukesh Agrawal, Mainak Chaudhuri | 2018-07-03 |
| 9921839 | Coordinated thread criticality-aware memory scheduling | Lavanya Subramanian, Nithiyanandan Bashyam, Anant Vithal Nori | 2018-03-20 |
| 9720829 | Online learning based algorithms to increase retention and reuse of GPU-generated dynamic surfaces in outer-level caches | Suresh Srinivasan, Rakesh Ramesh, Jayesh Gaur | 2017-08-01 |
| 9323678 | Identifying and prioritizing critical instructions within processor circuitry | Amit Kumar | 2016-04-26 |
| 9251096 | Data compression in processor caches | Jayesh Gaur, Alaa R. Alameldeen | 2016-02-02 |
| 9195606 | Dead block predictors for cooperative execution in the last level cache | Ragavendra Natarajan, Jayesh Guar, Nithiyanandan Bashyam, Mainak Chaudhuri | 2015-11-24 |
| 8667222 | Bypass and insertion algorithms for exclusive last-level caches | Jayesh Gaur, Mainak Chaudhuri | 2014-03-04 |
| 7577947 | Methods and apparatus to dynamically insert prefetch instructions based on garbage collector analysis and layout of objects | Mauricio J. Serrano, Richard L. Hudson, Ali-Reza Adl-Tabatabai | 2009-08-18 |
| 7490117 | Dynamic performance monitoring-based approach to memory management | Richard L. Hudson, Mauricio J. Serrano, Ali-Reza Adl-Tabatabai | 2009-02-10 |
| 7389385 | Methods and apparatus to dynamically insert prefetch instructions based on compiler and garbage collector analysis | Mauricio J. Serrano, Richard L. Hudson, Ali-Reza Adl-Tabatabai | 2008-06-17 |
| 7197521 | Method and system performing concurrently mark-sweep garbage collection invoking garbage collection thread to track and mark live objects in heap block using bit vector | Richard L. Hudson | 2007-03-27 |
| 6950837 | Method for using non-temporal streaming to improve garbage collection algorithm | Richard L. Hudson | 2005-09-27 |
| 6662274 | Method for using cache prefetch feature to improve garbage collection algorithm | Richard L. Hudson | 2003-12-09 |